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[94.29.39.224]) by smtp.gmail.com with ESMTPSA id u10sm2108661ljk.56.2020.03.19.13.53.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2020 13:53:23 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Laxman Dewangan , Vinod Koul , Dan Williams Cc: Wolfram Sang , linux-i2c@vger.kernel.org, linux-tegra@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/2] dmaengine: tegra-apb: Improve DMA synchronization Date: Thu, 19 Mar 2020 23:52:28 +0300 Message-Id: <20200319205228.8883-2-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200319205228.8883-1-digetx@gmail.com> References: <20200319205228.8883-1-digetx@gmail.com> MIME-Version: 1.0 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Boot CPU0 always handles DMA interrupts and under some rare circumstances it could stuck in uninterruptible state for a significant time (like in a case of KASAN + NFS root). In this case sibling CPU, which waits for DMA transfer completion, will get a DMA transfer timeout. In order to handle this rare condition, interrupt status needs to be polled until interrupt is handled. Signed-off-by: Dmitry Osipenko --- drivers/dma/tegra20-apb-dma.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c index 26f427e02369..d4a92714740c 100644 --- a/drivers/dma/tegra20-apb-dma.c +++ b/drivers/dma/tegra20-apb-dma.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "dmaengine.h" @@ -202,6 +203,8 @@ struct tegra_dma_channel { unsigned int slave_id; struct dma_slave_config dma_sconfig; struct tegra_dma_channel_regs channel_reg; + + struct wait_queue_head wq; }; /* tegra_dma: Tegra DMA specific information */ @@ -682,6 +685,7 @@ static irqreturn_t tegra_dma_isr(int irq, void *dev_id) tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status); tdc->isr_handler(tdc, false); tasklet_schedule(&tdc->tasklet); + wake_up_all(&tdc->wq); spin_unlock(&tdc->lock); return IRQ_HANDLED; } @@ -798,10 +802,29 @@ static int tegra_dma_terminate_all(struct dma_chan *dc) return 0; } +static bool tegra_dma_eoc_interrupt_deasserted(struct tegra_dma_channel *tdc) +{ + unsigned long flags; + u32 status; + + spin_lock_irqsave(&tdc->lock, flags); + status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); + spin_unlock_irqrestore(&tdc->lock, flags); + + return !(status & TEGRA_APBDMA_STATUS_ISE_EOC); +} + static void tegra_dma_synchronize(struct dma_chan *dc) { struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); + /* + * CPU, which handles interrupt, could be busy in + * uninterruptible state, in this case sibling CPU + * should wait until interrupt is handled. + */ + wait_event(tdc->wq, tegra_dma_eoc_interrupt_deasserted(tdc)); + tasklet_kill(&tdc->tasklet); } @@ -1495,6 +1518,7 @@ static int tegra_dma_probe(struct platform_device *pdev) tasklet_init(&tdc->tasklet, tegra_dma_tasklet, (unsigned long)tdc); spin_lock_init(&tdc->lock); + init_waitqueue_head(&tdc->wq); INIT_LIST_HEAD(&tdc->pending_sg_req); INIT_LIST_HEAD(&tdc->free_sg_req);