| Message ID | 20200528222401.26941-12-Sergey.Semin@baikalelectronics.ru (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | dmaengine: dw: Take Baikal-T1 SoC DW DMAC peculiarities into account | expand |
On Fri, May 29, 2020 at 01:24:01AM +0300, Serge Semin wrote: > Multi-block support provides a way to map the kernel-specific SG-table so > the DW DMA device would handle it as a whole instead of handling the > SG-list items or so called LLP block items one by one. So if true LLP > list isn't supported by the DW DMA engine, then soft-LLP mode will be > utilized to load and execute each LLP-block one by one. The soft-LLP mode > of the DMA transactions execution might not work well for some DMA > consumers like SPI due to its Tx and Rx buffers inter-dependency. Let's > initialize the max_sg_nents DMA channels capability based on the nollp > flag state. If it's true, no hardware accelerated LLP is available and > max_sg_nents should be set with 1, which means that the DMA engine > can handle only a single SG list entry at a time. If noLLP is set to > false, then hardware accelerated LLP is supported and the DMA engine > can handle infinite number of SG entries in a single DMA transaction. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> > Cc: Arnd Bergmann <arnd@arndb.de> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: linux-mips@vger.kernel.org > Cc: devicetree@vger.kernel.org > > --- > > Changelog v3: > - This is a new patch created as a result of the discussion with Vinud and > Andy in the framework of DW DMA burst and LLP capabilities. > > Changelog v4: > - Use explicit if-else statement when assigning the max_sg_nents field. > --- > drivers/dma/dw/core.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c > index 60ef779fc5e0..b76eee75fde8 100644 > --- a/drivers/dma/dw/core.c > +++ b/drivers/dma/dw/core.c > @@ -1059,6 +1059,18 @@ static void dwc_caps(struct dma_chan *chan, struct dma_slave_caps *caps) > struct dw_dma_chan *dwc = to_dw_dma_chan(chan); > > caps->max_burst = dwc->max_burst; > + > + /* > + * It might be crucial for some devices to have the hardware > + * accelerated multi-block transfers supported, aka LLPs in DW DMAC > + * notation. So if LLPs are supported then max_sg_nents is set to > + * zero which means unlimited number of SG entries can be handled in a > + * single DMA transaction, otherwise it's just one SG entry. > + */ > + if (dwc->nollp) > + caps->max_sg_nents = 1; > + else > + caps->max_sg_nents = 0; > } > > int do_dma_probe(struct dw_dma_chip *chip) > -- > 2.26.2 >
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index 60ef779fc5e0..b76eee75fde8 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -1059,6 +1059,18 @@ static void dwc_caps(struct dma_chan *chan, struct dma_slave_caps *caps) struct dw_dma_chan *dwc = to_dw_dma_chan(chan); caps->max_burst = dwc->max_burst; + + /* + * It might be crucial for some devices to have the hardware + * accelerated multi-block transfers supported, aka LLPs in DW DMAC + * notation. So if LLPs are supported then max_sg_nents is set to + * zero which means unlimited number of SG entries can be handled in a + * single DMA transaction, otherwise it's just one SG entry. + */ + if (dwc->nollp) + caps->max_sg_nents = 1; + else + caps->max_sg_nents = 0; } int do_dma_probe(struct dw_dma_chip *chip)
Multi-block support provides a way to map the kernel-specific SG-table so the DW DMA device would handle it as a whole instead of handling the SG-list items or so called LLP block items one by one. So if true LLP list isn't supported by the DW DMA engine, then soft-LLP mode will be utilized to load and execute each LLP-block one by one. The soft-LLP mode of the DMA transactions execution might not work well for some DMA consumers like SPI due to its Tx and Rx buffers inter-dependency. Let's initialize the max_sg_nents DMA channels capability based on the nollp flag state. If it's true, no hardware accelerated LLP is available and max_sg_nents should be set with 1, which means that the DMA engine can handle only a single SG list entry at a time. If noLLP is set to false, then hardware accelerated LLP is supported and the DMA engine can handle infinite number of SG entries in a single DMA transaction. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org --- Changelog v3: - This is a new patch created as a result of the discussion with Vinud and Andy in the framework of DW DMA burst and LLP capabilities. Changelog v4: - Use explicit if-else statement when assigning the max_sg_nents field. --- drivers/dma/dw/core.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)