| Message ID | 20200730154545.3965-4-Sergey.Semin@baikalelectronics.ru (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | dmaengine: dw: Introduce non-mem peripherals optimizations | expand |
On Thu, Jul 30, 2020 at 06:45:43PM +0300, Serge Semin wrote: > Indeed in case of the DMA_DEV_TO_MEM DMA transfers it's enough to take the > destination memory address and the destination master data width into > account to calculate the CTLx.DST_TR_WIDTH setting of the memory > peripheral. According to the DW DMAC IP-core Databook (page 66, Example 5) Always put a version of the Databook document. I have several and they may differ. > at the and of a DMA transfer when the DMA-channel internal FIFO is left > with data less than for a single destination burst transaction, the > destination peripheral will enter the Single Transaction Region where the > DW DMA controller can complete a block transfer to the destination using > single transactions (non-burst transaction of CTLx.DST_TR_WIDTH bytes). If > there is no enough data in the DMA-channel internal FIFO for even a single > non-burst transaction of CTLx.DST_TR_WIDTH bytes, then the channel enters > "FIFO flush mode". That mode is activated to empty the FIFO and flush the > leftovers out to the memory peripheral. The flushing procedure is simple. > The data is sent to the memory by means of a set of single transaction of > CTLx.SRC_TR_WIDTH bytes. To sum up it's redundant to use the LLPs length > to find out the CTLx.DST_TR_WIDTH parameter value, since each DMA transfer > will be completed with the CTLx.SRC_TR_WIDTH bytes transaction if it is > required. > In this commit we remove the LLP entry length from the statement which "In this commit" should be removed, see Submitting Patches ("This patch"). > calculates the memory peripheral DMA transaction width since it's > redundant due to the feature described above. By doing so we'll improve > the memory bus utilization and speed up the DMA-channel performance for > DMA_DEV_TO_MEM DMA-transfers. Okay, I have no objections. Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > --- > drivers/dma/dw/core.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c > index 4700f2e87a62..3da0aea9fe25 100644 > --- a/drivers/dma/dw/core.c > +++ b/drivers/dma/dw/core.c > @@ -723,7 +723,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, > lli_write(desc, sar, reg); > lli_write(desc, dar, mem); > lli_write(desc, ctlhi, ctlhi); > - mem_width = __ffs(data_width | mem | dlen); > + mem_width = __ffs(data_width | mem); > lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width)); > desc->len = dlen; > > -- > 2.27.0 >
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index 4700f2e87a62..3da0aea9fe25 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -723,7 +723,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, lli_write(desc, sar, reg); lli_write(desc, dar, mem); lli_write(desc, ctlhi, ctlhi); - mem_width = __ffs(data_width | mem | dlen); + mem_width = __ffs(data_width | mem); lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width)); desc->len = dlen;
Indeed in case of the DMA_DEV_TO_MEM DMA transfers it's enough to take the destination memory address and the destination master data width into account to calculate the CTLx.DST_TR_WIDTH setting of the memory peripheral. According to the DW DMAC IP-core Databook (page 66, Example 5) at the and of a DMA transfer when the DMA-channel internal FIFO is left with data less than for a single destination burst transaction, the destination peripheral will enter the Single Transaction Region where the DW DMA controller can complete a block transfer to the destination using single transactions (non-burst transaction of CTLx.DST_TR_WIDTH bytes). If there is no enough data in the DMA-channel internal FIFO for even a single non-burst transaction of CTLx.DST_TR_WIDTH bytes, then the channel enters "FIFO flush mode". That mode is activated to empty the FIFO and flush the leftovers out to the memory peripheral. The flushing procedure is simple. The data is sent to the memory by means of a set of single transaction of CTLx.SRC_TR_WIDTH bytes. To sum up it's redundant to use the LLPs length to find out the CTLx.DST_TR_WIDTH parameter value, since each DMA transfer will be completed with the CTLx.SRC_TR_WIDTH bytes transaction if it is required. In this commit we remove the LLP entry length from the statement which calculates the memory peripheral DMA transaction width since it's redundant due to the feature described above. By doing so we'll improve the memory bus utilization and speed up the DMA-channel performance for DMA_DEV_TO_MEM DMA-transfers. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> --- drivers/dma/dw/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)