| Message ID | 20210616105557.9321-1-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [v2] dt-bindings: dma: Document RZ/G2L bindings | expand |
Hi Biju, On Wed, Jun 16, 2021 at 1:14 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Document RZ/G2L DMAC bindings. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > Note:- This patch has dependency on #include <dt-bindings/clock/r9a07g044-cpg.h> file which will be in > next 5.14-rc1 release. > > v1->v2: > * Made interrupt names in defined order > * Removed src address and channel configuration from dma-cells. > * Changed the compatibele string to "renesas,r9a07g044-dmac". Thanks for the update! > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml > + interrupt-names: > + items: > + - const: ch0 > + - const: ch1 > + - const: ch2 > + - const: ch3 > + - const: ch4 > + - const: ch5 > + - const: ch6 > + - const: ch7 > + - const: ch8 > + - const: ch9 > + - const: ch10 > + - const: ch11 > + - const: ch12 > + - const: ch13 > + - const: ch14 > + - const: ch15 > + - const: error You may want to put the "error" interrupt first, like renesas,rcar-dmac.yaml does, to make life easier when the next SoC reuses this block, but with a different number of channels. With that fixed: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
On Wed, 16 Jun 2021 11:55:57 +0100, Biju Das wrote: > Document RZ/G2L DMAC bindings. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > Note:- This patch has dependency on #include <dt-bindings/clock/r9a07g044-cpg.h> file which will be in > next 5.14-rc1 release. > > v1->v2: > * Made interrupt names in defined order > * Removed src address and channel configuration from dma-cells. > * Changed the compatibele string to "renesas,r9a07g044-dmac". > * > v1:- > * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20210611113642.18457-2-biju.das.jz@bp.renesas.com/ > --- > .../bindings/dma/renesas,rz-dmac.yaml | 118 ++++++++++++++++++ > 1 file changed, 118 insertions(+) > create mode 100644 Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/dma/renesas,rz-dmac.example.dts:20:18: fatal error: dt-bindings/clock/r9a07g044-cpg.h: No such file or directory 20 | #include <dt-bindings/clock/r9a07g044-cpg.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/dma/renesas,rz-dmac.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1416: dt_binding_check] Error 2 \ndoc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1492896 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH v2] dt-bindings: dma: Document RZ/G2L bindings > > Hi Biju, > > On Wed, Jun 16, 2021 at 1:14 PM Biju Das <biju.das.jz@bp.renesas.com> > wrote: > > Document RZ/G2L DMAC bindings. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > Note:- This patch has dependency on #include > > <dt-bindings/clock/r9a07g044-cpg.h> file which will be in next 5.14-rc1 > release. > > > > v1->v2: > > * Made interrupt names in defined order > > * Removed src address and channel configuration from dma-cells. > > * Changed the compatibele string to "renesas,r9a07g044-dmac". > > Thanks for the update! > > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml > > > + interrupt-names: > > + items: > > + - const: ch0 > > + - const: ch1 > > + - const: ch2 > > + - const: ch3 > > + - const: ch4 > > + - const: ch5 > > + - const: ch6 > > + - const: ch7 > > + - const: ch8 > > + - const: ch9 > > + - const: ch10 > > + - const: ch11 > > + - const: ch12 > > + - const: ch13 > > + - const: ch14 > > + - const: ch15 > > + - const: error > > You may want to put the "error" interrupt first, like renesas,rcar- > dmac.yaml does, to make life easier when the next SoC reuses this block, > but with a different number of channels. Sure. will fix this in V3. > > With that fixed: > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux- > m68k.org > > In personal conversations with technical people, I call myself a hacker. > But when I'm talking to journalists I just say "programmer" or something > like that. > -- Linus Torvalds
diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml new file mode 100644 index 000000000000..0389050aadf6 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L DMA Controller + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + items: + - enum: + - renesas,r9a07g044-dmac # RZ/G2{L,LC} + - const: renesas,rz-dmac + + reg: + items: + - description: Control and channel register block + - description: DMA extended resource selector block + + interrupts: + maxItems: 17 + + interrupt-names: + items: + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 + - const: error + + clocks: + maxItems: 1 + + '#dma-cells': + const: 1 + description: + The cell specifies the MID/RID of the DMAC port connected to + the DMA client. + + dma-channels: + const: 16 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - '#dma-cells' + - dma-channels + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/r9a07g044-cpg.h> + + dmac: dma-controller@11820000 { + compatible = "renesas,r9a07g044-dmac", + "renesas,rz-dmac"; + reg = <0x11820000 0x10000>, + <0x11830000 0x10000>; + interrupts = <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "error"; + clocks = <&cpg CPG_MOD R9A07G044_CLK_DMAC>; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_CLK_DMAC>; + #dma-cells = <1>; + dma-channels = <16>; + };