From patchwork Thu Nov 25 09:00:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12638743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97CA9C433EF for ; Thu, 25 Nov 2021 09:03:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354022AbhKYJG2 (ORCPT ); Thu, 25 Nov 2021 04:06:28 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:62178 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344142AbhKYJE1 (ORCPT ); Thu, 25 Nov 2021 04:04:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1637830876; x=1669366876; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WIpbBPu+LDILnDfRZxv4mO7fUQqnAghfChRhfJnCk4s=; b=iPiRmHIgft2ri8SLuK3BrKZCbxAUW4zNGBfNfRcwJ00x4CErLzrI5cCP NM/nnpyxdcgxqa69b/an5y8fG6O8r3rr+EklnTbPZP/JwGy+w/JCpvm4B Xp5x+Rx3+lIcGI+viNpGXVC9NCSC6GqyiO7qaEnOGHpE/hKXtdSMx4YAl y70wafsT3P1Wyi24Su96JeE++1sBeBlN9qT40xWTx3V9j7Bag7YsrLXZF 9zR8P9T+PYzrd949eNFs+4zjSxZJTSMBz7QY91Jq6iySTtbA35FmTDBa8 0aQIe4hLUngnOQFttu4B0OQQugZERVsvqSrTEqPKfqBA2tu9NMlJUkAgN A==; IronPort-SDR: //kzR0pxn4N+VaD4Z8z0EdlDuYPhJSoF+S51vq0dm61RulaDTUFU4DZ2M3n6uwUkjBLxkuQvrf /SFK4yBtSs9DmwvBjTOk3+iWlDTFnWGmqWqIjxPJ/102XWMRWen4iT2MwGKyGKKGaRKVOYLten kBagW/bMEoQHSPD2oGoHAm3NtEPZSFJ6zFeM4f4a+R8SwiZBasovecpAqyG42HljyaxdgF+Hlm oCWw22YhU98WeUncsC9t6fd/LJOG8UJWNh1Gf+UOg8u8DLwXyhRKRt3aJsPsUQGgeJREEqRILc wS1DPhpoYz/mbhftS3cK6oTc X-IronPort-AV: E=Sophos;i="5.87,262,1631602800"; d="scan'208";a="144534284" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 Nov 2021 02:01:16 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 25 Nov 2021 02:01:09 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 25 Nov 2021 02:01:06 -0700 From: Tudor Ambarus To: , , , , CC: , , , , , , , Tudor Ambarus Subject: [PATCH v2 11/13] dmaengine: at_xdmac: Fix lld view setting Date: Thu, 25 Nov 2021 11:00:26 +0200 Message-ID: <20211125090028.786832-12-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211125090028.786832-1-tudor.ambarus@microchip.com> References: <20211125090028.786832-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org AT_XDMAC_CNDC_NDVIEW_NDV3 was set even for AT_XDMAC_MBR_UBC_NDV2, because of the wrong bit handling. Fix it. Fixes: ee0fe35c8dcd ("dmaengine: xdmac: Handle descriptor's view 3 registers") Signed-off-by: Tudor Ambarus --- drivers/dma/at_xdmac.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index 89d0fc229d68..ba2fe383fa5e 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -99,6 +99,7 @@ #define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */ #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */ #define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */ +#define AT_XDMAC_CNDC_NDVIEW_MASK GENMASK(28, 27) #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */ #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */ #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */ @@ -402,7 +403,8 @@ static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan, */ if (at_xdmac_chan_is_cyclic(atchan)) reg = AT_XDMAC_CNDC_NDVIEW_NDV1; - else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3) + else if ((first->lld.mbr_ubc & + AT_XDMAC_CNDC_NDVIEW_MASK) == AT_XDMAC_MBR_UBC_NDV3) reg = AT_XDMAC_CNDC_NDVIEW_NDV3; else reg = AT_XDMAC_CNDC_NDVIEW_NDV2;