From patchwork Wed Dec 15 11:01:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12678047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF9C4C433EF for ; Wed, 15 Dec 2021 11:01:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241915AbhLOLB7 (ORCPT ); Wed, 15 Dec 2021 06:01:59 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:16372 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241945AbhLOLBr (ORCPT ); Wed, 15 Dec 2021 06:01:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1639566106; x=1671102106; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8RYbGapbxedXgpRLmZEbbzAVzO7YuLjgxhiAaZYRrrQ=; b=tVMyev2mQUOBD+OlXmhZpCkGhhegPmbQHvLjqValBMZJZkFzUUgdi02z 2XwH6QIIZffnCzay788wK0ZBnnzujVg8bRYk2WuuPJj3/8qJ+UJ+p4fqX JgD7eMvc4JG9fcVa7otkwLgEKM09WLQhvoHhVEtROTxpo5LBJwUNDBlI8 lmX83idgEE/dMYUThn+7ahksOgMySxluwFMb+1XMTDJc3iQ9IuDoWA+J/ 3JBwHhfV4MXaMlFuw7HiwsJzn0Gd5MAYYzdGbS7fuHc/zj6L8RUZypOnf P/M+Qqe/X2XzS2mciXdSq4HYk+zkbxsp6nT1SW93WhwLnbf/yhCeTYSAE w==; IronPort-SDR: bPjJrCgEAhaWqGBOXZUmFz/AXofXvRlH40bZwQRZtjEoICIRpJl0pk76Jekwyua1Qq5mi/dje0 ay01HCpO4GE5xIV09wy5UHyLFGn9DWT5N39mdHL2tMkixOb1NfzEsgHxbKeGq2xLYNdYKFo6xt 2CTuSf6vcpkNE1kc4/J+oRNWwtmTF8L1GFKzJmVG66yBXxEeC6/quDVnGwIFotj5alTKIGWkL1 sC4z9s8wj88Aexo6Y8gRZCMec+Ac2Qbm1RNnrzIaj1jO37v6V5MnqLxumzSEeEdi2TdWqvdLbx cr2zZpz99zBG9c7OQ07VprIM X-IronPort-AV: E=Sophos;i="5.88,207,1635231600"; d="scan'208";a="139842714" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 15 Dec 2021 04:01:46 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 15 Dec 2021 04:01:45 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 15 Dec 2021 04:01:43 -0700 From: Tudor Ambarus To: CC: , , , , , , Tudor Ambarus Subject: [PATCH v3 10/12] dmaengine: at_xdmac: Fix at_xdmac_lld struct definition Date: Wed, 15 Dec 2021 13:01:13 +0200 Message-ID: <20211215110115.191749-11-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211215110115.191749-1-tudor.ambarus@microchip.com> References: <20211215110115.191749-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The hardware channel next descriptor view structure contains just fields of 32 bits, while dma_addr_t can be of type u64 or u32 depending on CONFIG_ARCH_DMA_ADDR_T_64BIT. Force u32 to comply with what the hardware expects. Fixes: e1f7c9eee707 ("dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver") Signed-off-by: Tudor Ambarus --- drivers/dma/at_xdmac.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index 6e5bfc9b3825..abe8c4615e65 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -253,15 +253,15 @@ struct at_xdmac { /* Linked List Descriptor */ struct at_xdmac_lld { - dma_addr_t mbr_nda; /* Next Descriptor Member */ - u32 mbr_ubc; /* Microblock Control Member */ - dma_addr_t mbr_sa; /* Source Address Member */ - dma_addr_t mbr_da; /* Destination Address Member */ - u32 mbr_cfg; /* Configuration Register */ - u32 mbr_bc; /* Block Control Register */ - u32 mbr_ds; /* Data Stride Register */ - u32 mbr_sus; /* Source Microblock Stride Register */ - u32 mbr_dus; /* Destination Microblock Stride Register */ + u32 mbr_nda; /* Next Descriptor Member */ + u32 mbr_ubc; /* Microblock Control Member */ + u32 mbr_sa; /* Source Address Member */ + u32 mbr_da; /* Destination Address Member */ + u32 mbr_cfg; /* Configuration Register */ + u32 mbr_bc; /* Block Control Register */ + u32 mbr_ds; /* Data Stride Register */ + u32 mbr_sus; /* Source Microblock Stride Register */ + u32 mbr_dus; /* Destination Microblock Stride Register */ }; /* 64-bit alignment needed to update CNDA and CUBC registers in an atomic way. */