From patchwork Fri Jul 1 19:22:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12903649 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DF13C43334 for ; Fri, 1 Jul 2022 19:24:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232248AbiGATYx (ORCPT ); Fri, 1 Jul 2022 15:24:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232160AbiGATYw (ORCPT ); Fri, 1 Jul 2022 15:24:52 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B9A031238; Fri, 1 Jul 2022 12:24:45 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 616C6CE33DD; Fri, 1 Jul 2022 19:24:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4B0BBC341CD; Fri, 1 Jul 2022 19:24:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656703481; bh=Hx5muWw17Jb0oqDiAd8+qbBnr1W1BbGEsr7q+7oKh+o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Lnc/A97NcUj3poedeyd4maMRBOzjDxYynybF3AhzHkmX2+PNvDX93LK+Dye2Tcfhj W6F9KzI6TN0ISSmu0RU6HprkI/hGEfMl17gHrSMnrJ/XtnmhScTeuA7ncJCsdepcLD mMIjE2XVvGLH8k3sNm7/686bkqm4q13pOYY4gbcL/EnI5gUgbxjBXaDKubCEO8QcZm cCFSv2FwS5A3KzfVx1XgWb+YP2U5Td1PrrW6Rz3c1DZzJiiVBkm9bLkYWcQL36LI7u b+oeZ4rFcUotmSlv62g8y71lrbVka0o9HStErLS965dX5IokL8STNI8rJMIwGv/bTL 6cewHuFvVD+kw== From: Conor Dooley To: David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Thierry Reding , Sam Ravnborg , Eugeniy Paltsev , Vinod Koul , Liam Girdwood , Mark Brown , Serge Semin , Daniel Lezcano , Palmer Dabbelt , Palmer Dabbelt Cc: Paul Walmsley , Albert Ou , Conor Dooley , Masahiro Yamada , Damien Le Moal , Geert Uytterhoeven , Niklas Cassel , Dillon Min , Jose Abreu , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, alsa-devel@alsa-project.org, linux-riscv@lists.infradead.org Subject: [PATCH v4 11/14] riscv: dts: canaan: remove spi-max-frequency from controllers Date: Fri, 1 Jul 2022 20:22:57 +0100 Message-Id: <20220701192300.2293643-12-conor@kernel.org> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220701192300.2293643-1-conor@kernel.org> References: <20220701192300.2293643-1-conor@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org From: Conor Dooley spi-max-frequency is a device, not a controller property and should be removed. Link: https://lore.kernel.org/lkml/20220526014141.2872567-1-robh@kernel.org/ Tested-by: Niklas Cassel Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/canaan/k210.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 900dc629a945..948dc235e39d 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -451,7 +451,6 @@ spi0: spi@52000000 { clock-names = "ssi_clk", "pclk"; resets = <&sysrst K210_RST_SPI0>; reset-names = "spi"; - spi-max-frequency = <25000000>; num-cs = <4>; reg-io-width = <4>; }; @@ -467,7 +466,6 @@ spi1: spi@53000000 { clock-names = "ssi_clk", "pclk"; resets = <&sysrst K210_RST_SPI1>; reset-names = "spi"; - spi-max-frequency = <25000000>; num-cs = <4>; reg-io-width = <4>; }; @@ -483,8 +481,7 @@ spi3: spi@54000000 { clock-names = "ssi_clk", "pclk"; resets = <&sysrst K210_RST_SPI3>; reset-names = "spi"; - /* Could possibly go up to 200 MHz */ - spi-max-frequency = <100000000>; + num-cs = <4>; reg-io-width = <4>; };