From patchwork Fri Jul 29 10:44:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 12932308 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81E3DC25B0E for ; Fri, 29 Jul 2022 10:45:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235818AbiG2KpA (ORCPT ); Fri, 29 Jul 2022 06:45:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235742AbiG2Ko7 (ORCPT ); Fri, 29 Jul 2022 06:44:59 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1171083211; Fri, 29 Jul 2022 03:44:58 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B1F976601B67; Fri, 29 Jul 2022 11:44:55 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1659091496; bh=yVmhhT/qx+tW3CwtsNMyM1l565LqcHdXD5WPr7UhHvw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IAY6rFWWe4TWdsu6dYjxm9mvBCzXlLn949L17cmUizMmPbLMDKq7fOdlugwx2wB/y FNWW4BNaZ1TsF32t3jztQX0+00XsR/OIJidBhdy4UCfnesSEcAmEjzWKerWBpvXZBX EfeRj9TNfW4pmDeBZ1MIv//2YQqu/dvlz1kcwg8qUy6aNbxpnvj0W1bJPOiAdCK8jT KBRqaEd3MjStG4xu5EPf252jg6ChlHcdcr3E7vL9Y0ZgfV5TtPWpOmkvnwopFULyGr dXdRWC1aWRQp+8zEvYnsHvHqdGkferWs4G6EzI8dWc74eRnWmSN8W0VgjW9x7ClXmG 4ztQmf85X8law== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, fparent@baylibre.com, sam.shih@mediatek.com, sean.wang@mediatek.com, long.cheng@mediatek.com, wenbin.mei@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht Subject: [PATCH 4/8] arm64: dts: mediatek: mt6795: Replace UART dummy clocks with pericfg Date: Fri, 29 Jul 2022 12:44:36 +0200 Message-Id: <20220729104441.39177-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> References: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The UART nodes had a dummy clock for early bringup, as it is expected that these are left on by the bootloader: now that the pericfg clock controller is supported, we can replace them with the real clocks. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 9166d481a366..559fec1ee123 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -312,7 +312,8 @@ uart0: serial@11002000 { "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = ; - clocks = <&clk26m>; + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -321,7 +322,8 @@ uart1: serial@11003000 { "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = ; - clocks = <&clk26m>; + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -330,7 +332,8 @@ uart2: serial@11004000 { "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = ; - clocks = <&clk26m>; + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -339,7 +342,8 @@ uart3: serial@11005000 { "mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x400>; interrupts = ; - clocks = <&clk26m>; + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; + clock-names = "baud", "bus"; status = "disabled"; }; };