From patchwork Sat Aug 20 12:57:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 12949655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D848C32796 for ; Sat, 20 Aug 2022 12:59:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347156AbiHTM7Y (ORCPT ); Sat, 20 Aug 2022 08:59:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346831AbiHTM7A (ORCPT ); Sat, 20 Aug 2022 08:59:00 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 371A148EB2; Sat, 20 Aug 2022 05:58:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661000311; x=1692536311; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0AgovvAf2oyRX/MLTme3uR4QecLpUDkruVyWCc1dDvg=; b=eBeWNbZjadPwfQTKUEzx1EFEdDad7K6099uGMX60+SGRrAxRopMSWaPD 2XePLzEYjiLhMnLIXYUVMeCs336Uea77RmgM0yF2ojB0XMYarPRPnrN1w meoaztD3BrpihaVPpcNid5CWd/CtwzUWiHgLG1ysjd7k5wPr5wom+MZuN Fn2pFXnsJ4FqoJAcMEu1r44s4AfWFykNG4sZfqTz/VCjUsinGvu5mdYMV mZ5F7PheE3zYJkD3TFwEY32FXYm0j38fRgSF+hI6cY2yaIK2/hn4+vp9G 9xGWL/dEZ1uC8yqVXuQNWkIFd2gO434Y/ZNi9x25Nhe3Jwyl1k7aDZ10V w==; X-IronPort-AV: E=Sophos;i="5.93,251,1654585200"; d="scan'208";a="109911618" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Aug 2022 05:58:29 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Sat, 20 Aug 2022 05:58:29 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Sat, 20 Aug 2022 05:58:25 -0700 From: Tudor Ambarus To: , , , CC: , , , , , , , , , , Subject: [PATCH 19/33] dmaengine: at_hdmac: Don't allow CPU to reorder channel enable Date: Sat, 20 Aug 2022 15:57:03 +0300 Message-ID: <20220820125717.588722-20-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220820125717.588722-1-tudor.ambarus@microchip.com> References: <20220820125717.588722-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org at_hdmac uses __raw_writel for register writes. In the absence of a barrier, the CPU may reorder the register operations. Introduce a write memory barrier so that the CPU does not reorder the channel enable, thus the start of the transfer, without making sure that all the pre-required register fields are already written. Fixes: dc78baa2b90b ("dmaengine: at_hdmac: new driver for the Atmel AHB DMA Controller") Reported-by: Peter Rosin Cc: stable@vger.kernel.org Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/lkml/13c6c9a2-6db5-c3bf-349b-4c127ad3496a@axentia.se/ --- drivers/dma/at_hdmac.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c index 825a29ede35e..1cb0d26d30ed 100644 --- a/drivers/dma/at_hdmac.c +++ b/drivers/dma/at_hdmac.c @@ -691,6 +691,8 @@ static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) channel_writel(atchan, DPIP, FIELD_PREP(ATC_DPIP_HOLE, first->dst_hole) | FIELD_PREP(ATC_DPIP_BOUNDARY, first->boundary)); + /* Don't allow CPU to reorder channel enable. */ + wmb(); dma_writel(atdma, CHER, atchan->mask); vdbg_dump_regs(atchan);