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[83.9.31.195]) by smtp.gmail.com with ESMTPSA id y23-20020a2e7d17000000b002b94b355527sm2602662ljc.32.2023.08.30.05.48.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Aug 2023 05:48:51 -0700 (PDT) From: Konrad Dybcio Date: Wed, 30 Aug 2023 14:48:43 +0200 Subject: [PATCH 4/7] arm64: dts: qcom: sm8550: Mark QUPs and GPI dma-coherent MIME-Version: 1.0 Message-Id: <20230830-topic-8550_dmac2-v1-4-49bb25239fb1@linaro.org> References: <20230830-topic-8550_dmac2-v1-0-49bb25239fb1@linaro.org> In-Reply-To: <20230830-topic-8550_dmac2-v1-0-49bb25239fb1@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abel Vesa , Neil Armstrong , Sai Prakash Ranjan , Vinod Koul Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1693399725; l=1550; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=KpP1uTJWmiR9lXNPKL0Q4ECVHINhEgm+GZ5ZKetVnSM=; b=+dD2d2XMnFSAp9IluhmgTkJG4at8z79Ut86xE2lm9psXhU19uVuohOEECjdUPhFsFNgj2V/cY 3ys4iS9J/wyBllOhvAgptcW3SEJmrfB+je1ZLzPBHAIDsQFkB1eiWyO X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org These peripherals are DMA-coherent on 8550. Mark them as such. Interestingly enough, the I2C master hubs are not. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index c21ba6afa752..d1911b2f0bf3 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -809,6 +809,7 @@ gpi_dma2: dma-controller@800000 { dma-channels = <12>; dma-channel-mask = <0x3e>; iommus = <&apps_smmu 0x436 0>; + dma-coherent; status = "disabled"; }; @@ -820,6 +821,7 @@ qupv3_id_1: geniqup@8c0000 { clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; iommus = <&apps_smmu 0x423 0>; + dma-coherent; #address-cells = <2>; #size-cells = <2>; status = "disabled"; @@ -1305,6 +1307,7 @@ gpi_dma1: dma-controller@a00000 { dma-channels = <12>; dma-channel-mask = <0x1e>; iommus = <&apps_smmu 0xb6 0>; + dma-coherent; status = "disabled"; }; @@ -1318,6 +1321,7 @@ qupv3_id_0: geniqup@ac0000 { iommus = <&apps_smmu 0xa3 0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; interconnect-names = "qup-core"; + dma-coherent; #address-cells = <2>; #size-cells = <2>; status = "disabled";