[4/4] arm64: dts: imx93: Fix EDMA transfer failure

Commit Message

Frank Li Nov. 14, 2023, 3:48 p.m. UTC

The EDMAv4 has hardware restrictions, requiring some channels to be
allocated to ODD and others to EVEN. The previous eDMA driver did not
account for these restrictions, and it worked due to the order in dts
matching the requirements. The commit below reverts the rx/tx channel,
triggering this issue.

Adds channel requirements to the dts to instruct the driver to allocate
odd or even channels, ensuring it is not dependent on the order of rx/tx in
dts.

Fixes: a725990557e7 ("arm64: dts: imx93: Fix the dmas entries order")
Signed-off-by: Frank Li <[e-mail]>
---
 arch/arm64/boot/dts/freescale/imx93.dtsi | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
index ceccf47664407..6f06ebdcb2513 100644
--- a/arch/arm64/boot/dts/freescale/imx93.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
@@ -4,6 +4,7 @@ 
  */
 
 #include <dt-bindings/clock/imx93-clock.h>
+#include <dt-bindings/dma/fsl-edma.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -670,7 +671,8 @@  lpuart3: serial@42570000 {
 				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPUART3_GATE>;
 				clock-names = "ipg";
-				dmas = <&edma2 18 0 1>, <&edma2 17 0 0>;
+				dmas = <&edma2 18 0 (FSL_EDMA_RX | FSL_EDMA_ODD_CH)>,
+				       <&edma2 17 0 FSL_EDMA_EVEN_CH>;
 				dma-names = "rx", "tx";
 				status = "disabled";
 			};
@@ -681,7 +683,8 @@  lpuart4: serial@42580000 {
 				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPUART4_GATE>;
 				clock-names = "ipg";
-				dmas = <&edma2 20 0 1>, <&edma2 19 0 0>;
+				dmas = <&edma2 20 0 (FSL_EDMA_RX | FSL_EDMA_ODD_CH)>,
+				       <&edma2 19 0 FSL_EDMA_EVEN_CH>;
 				dma-names = "rx", "tx";
 				status = "disabled";
 			};
@@ -692,7 +695,8 @@  lpuart5: serial@42590000 {
 				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPUART5_GATE>;
 				clock-names = "ipg";
-				dmas = <&edma2 22 0 1>, <&edma2 21 0 0>;
+				dmas = <&edma2 22 0 (FSL_EDMA_RX | FSL_EDMA_ODD_CH)>,
+				       <&edma2 21 0 FSL_EDMA_EVEN_CH>;
 				dma-names = "rx", "tx";
 				status = "disabled";
 			};
@@ -703,7 +707,8 @@  lpuart6: serial@425a0000 {
 				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPUART6_GATE>;
 				clock-names = "ipg";
-				dmas = <&edma2 24 0 1>, <&edma2 23 0 0>;
+				dmas = <&edma2 24 0 (FSL_EDMA_RX | FSL_EDMA_ODD_CH)>,
+				       <&edma2 23 0 FSL_EDMA_EVEN_CH>;
 				dma-names = "rx", "tx";
 				status = "disabled";
 			};