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Tue, 21 May 2024 04:08:52 -0700 From: Sameer Pujar To: , , , , , , , CC: , , , , Subject: [RESEND PATCH 1/2] dt-bindings: dma: Add reg-names to nvidia,tegra210-adma Date: Tue, 21 May 2024 11:08:00 +0000 Message-ID: <20240521110801.1692582-2-spujar@nvidia.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240521110801.1692582-1-spujar@nvidia.com> References: <20240521110801.1692582-1-spujar@nvidia.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE37:EE_|CH3PR12MB7498:EE_ X-MS-Office365-Filtering-Correlation-Id: 88624823-684d-4928-3c55-08dc798670a5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|376005|82310400017|36860700004; X-Microsoft-Antispam-Message-Info: 7OaVWjtGNsQpu+XFUFEsIwG9ONxulHibZgcl73k0JeH7VbVaVhKlapQFoIzBk3NJ8z5+Q5PdDPzbYAvw1LXsP3rfVAIh4OZCWwuqHEIq6Fk9oKEfC2qHBOCtSLBpMenMuOJZ0nikEK9gdcFschySlRq3e1BH9MmMU27UYrwXMH1mF9cw4bznJ/HNTS4oFYzUElkZNhlI1xy57IBBGITqWTh1713LR+UAIe0/hngN5lrCa5AQcBT1l6Fulkx/mncXoO+VQKGFRvhADzN+f0pbT8H0ODYGR29+PFdL+GD4FJdGJivlPuCU4IPxnD9vEm/1WufBCzMR8ztyahSlApbBn1/6TfxX93ewkkys8kAMBnWCQWXui11RCjpsBblW77cNM5bvBB+yzfVeFnjbyqoSKRU9Pisqpo/ekb3245Kp05X7qI9vCekdveomqlZgNmPVmD9RVAnshNgGpm2fEd6Ujx9CPf4pdStGg/+domH80Tf1l16gyNWYBAoWfH3L8bCBidqOc95cTWP8vw46FlfeBX/vXspof5ts0KIsO/e/H12MYFY9sY1SSmmvNNfh1fB94YueQErHbNjNnhmpi5gql9tiRVEejEOuL9AIXUibW0ZFnTdqhrOpuidLhEMbEtj7l2otp0P0IBEwroLuMHWGp889omcHI3lKmMOQqSlsFOrzxQSJECJTYHn3vr2hkXCpckvCZEWJhzJr+Qtcu+xFyhlc0s3D+qs0RW7iWb4dpezfWMX5rkgF4yduzd/pjIAS/YzYrYGfz9uZAXJbdCjClJ15rWaVMnpGQlPdH4S3ilurMi8FvU482Hr5BX3iCJ1ov3cJ18fPfS7fHnNelIxsGLmogPqq4bt/iQpBjbKScOIsfDbZa0KX4YIglGst9TvGSqQFC7iVq88kGgmfitnqJMwJVyoWz+3ll2BlDHi+BC/D/KxtmIDHLXEHFznYJuXpXJc5zv48AAeJ2DV23Tvd68d3auI72SNAWMuu/BcOu6GWcD8EjEkmQ4y9fEVxBJTY35In5kqoykg9d+IxzfCP7kvGg9oK6w9X+t981KoO7aGqnbaZw0gSJJlHN875ZeQIIkGychRJqDydzG9AcjsgwR9nQHewhRnCDrs8k9r3nYNtQJqdEuXixzqVsfvCWFUDgOTe7GBWaVDe0JakmQFi9AqjxS2w1IIN81arTtaqo+tBdwwDcLQ/InXuKvsIlhFstXG6vv3caB9uxM912pFAm/jyoz4OjsnQTuB0GLAc5zGWH1LeLJgFzzhXFd41FnXTOKf9InrkFBR+YPyneWYBFar5eEBCKUdEXAfVfiCgCKZ/TLSaEuv0nOFFwvOyeZabPtte1GONLSEOWQwhw+kL1Esi05QkTaf1l0ZHVOQchx/8pl6hncPmgch9/DYbF2VD X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(1800799015)(376005)(82310400017)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2024 11:09:10.1093 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 88624823-684d-4928-3c55-08dc798670a5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE37.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7498 From: Mohan Kumar For Non-Hypervisor mode, Tegra ADMA driver requires the register resource range to include both global and channel page in the reg entry. For Hypervisor more, Tegra ADMA driver requires only the channel page and global page range is not allowed for access. Add reg-names DT binding for Hypervisor mode to help driver to differentiate the config between Hypervisor and Non-Hypervisor mode of execution. Signed-off-by: Mohan Kumar Signed-off-by: Sameer Pujar --- .../devicetree/bindings/dma/nvidia,tegra210-adma.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index 877147e95ecc..ede47f4a3eec 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -29,8 +29,18 @@ properties: - const: nvidia,tegra186-adma reg: + description: | + For hypervisor mode, the address range should include a + ADMA channel page address range, for non-hypervisor mode + it starts with ADMA base address covering Global and Channel + page address range. maxItems: 1 + reg-names: + description: only required for Hypervisor mode. + items: + - const: vm + interrupts: description: | Should contain all of the per-channel DMA interrupts in