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Tue, 21 May 2024 04:08:53 -0700 From: Sameer Pujar To: , , , , , , , CC: , , , , Subject: [RESEND PATCH 2/2] dmaengine: tegra210-adma: Add support for ADMA virtualization Date: Tue, 21 May 2024 11:08:01 +0000 Message-ID: <20240521110801.1692582-3-spujar@nvidia.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240521110801.1692582-1-spujar@nvidia.com> References: <20240521110801.1692582-1-spujar@nvidia.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC5:EE_|SN7PR12MB7107:EE_ X-MS-Office365-Filtering-Correlation-Id: 3730ad5a-f450-494e-1a25-08dc79866f87 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|36860700004|376005|1800799015; X-Microsoft-Antispam-Message-Info: vG9RtAQdHqaoZSzlgR2gH/kdxezuUUipNC6TVpGPrA1MeatmCNJchn++zdLPrfrjw9wSJwv8BlryiAmWDPz5E7mCadYwZPCtVANItsNCo7cTNeK8Nic6ZgHhzTpsd5Nq7Ji/EcZrheLh99Drm5RPdAIXuB6AjSsQoGoNl5ljLSpHSAtBKOtKE6vXLD6cdq/Ruv+bzVMBVsG+oig6FQptev2eL/MFKYu4BHkFq1JLm1NxYzzx0Y795lugcwaKcfYbYbMYf63X7G7JAFeKtj4XuuCaALsVWo8MO9D4r8RvqaptIvjSTooKu1oyt5hBf4t/jr4L/LmiBnV/XtvCel6DDvLr2sW2xSCglBIeBdmz2Zia5fGVeZ6pl3fsNQ2iTgTTOnNVNKrzz9g0KlyHdOywjlb5ZQnR6M7uscLUDvHfhH48nQP+u5xaoQ+dIJIkLeusw0WuvDIs1tA6wh5fHuohcEJsIOTkru+kpvXgImAtw68cBIULannnd3ShHzlmr99I0gKopgks4WhZ0eSNT8ON0HG+wjjUMaHzZm4cIZ/IJw9rDWRNqxNJxRCOPWHEXhXd5DZK/IoAKXfFDTU+TFfkMBsBA2Mtgx+3bRRTp8nCOHYGN35f8dMMHRVnQYQXEZqEGhKYt05yasDlccXm00ayGylizWBnFY+mAJjIWNTY8EaEsW8f66wA8VJ8YF1VqQsS53Oqb5q8tyz/i/5qSuSvxXKLMEsf5tjwKnoI4T4SLGRXvjbKheLRRGELDEdyYkteaIFjWbgfrR/CFbteLXcazN4ioDsMvVncr0N3OXNQwJogS4M5VBga9ieVfWsvbz+uC1Iu+Ive350QouyUPdAoKayavN78E6HcoDnj/TVC3hjdXAyF+cPmyatVMD9y4kqahW1oCHMIbA6HEGOxGsnPazDNYs0PnS+tmP3fqR1uQXKlGS6Rcxz6TeAyJV3nXjyAKFWkqjgLLSKEQCexKRJuDmuBbYPnWbaZQXaM3Tvs4w/5yh88MfXeeRQ+7YlSyZ4rn0G3u/wD1qJiR9tNPA6ftSacWPi+JfZRmVeitymlakHZOrIZpXDFAjVN0LBW1EzL03VZxAy94fsEKyUmHlFj6rZF9xmJ/eVD60haJYCXH1ifx9Lfe/ecqSsz1xjeVnkoJqFXo825fkIXU0BYQ53AnilgyicjJw0wAQ1Ef7mnvsrpm1lTHXU8KQgRpMh6jrvSmnM21bV62KJE2YABVfjp/uLUmqVis6x3A2tT2HQ6hhkJW24zoJl2A+6TzGSMBeK7IKYeF4nYYk2ZOebOSxMUugfbxz6Tuq/qnVY4g8inQj474wb7s0IoGRBZqyxuIhIUzfQIdl5r3LjQJ/8BnohGeTOQfSlgGrZmQWoOTC8NVWo= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(82310400017)(36860700004)(376005)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2024 11:09:08.1908 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3730ad5a-f450-494e-1a25-08dc79866f87 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7107 From: Mohan Kumar Tegra ADMA HW supports multiple PAGES for virtualization, to support virtualization support reg-names property has been added to DT binding to know the hypervisor mode. Also in hypervisor mode the ADMA global registers are not accessed by guest OS. Signed-off-by: Mohan Kumar Signed-off-by: Sameer Pujar --- drivers/dma/tegra210-adma.c | 44 ++++++++++++++++++++++++++++++------- 1 file changed, 36 insertions(+), 8 deletions(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index 24ad7077c53b..92f1c0c949dd 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -160,6 +160,8 @@ struct tegra_adma { /* Used to store global command register state when suspending */ unsigned int global_cmd; + bool is_virtualized; + const struct tegra_adma_chip_data *cdata; /* Last member of the structure */ @@ -222,8 +224,15 @@ static int tegra_adma_init(struct tegra_adma *tdma) u32 status; int ret; - /* Clear any interrupts */ - tdma_write(tdma, tdma->cdata->ch_base_offset + tdma->cdata->global_int_clear, 0x1); + if (!tdma->is_virtualized) { + /* Clear any interrupts */ + tdma_write(tdma, tdma->cdata->ch_base_offset + tdma->cdata->global_int_clear, 0x1); + } else { + /* For virtualized mode, ADMA global registers are not accessed */ + tdma_write(tdma, tdma->cdata->global_int_clear, 0x1); + tdma->global_cmd = 1; + return 0; + } /* Assert soft reset */ tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1); @@ -736,7 +745,9 @@ static int __maybe_unused tegra_adma_runtime_suspend(struct device *dev) struct tegra_adma_chan *tdc; int i; - tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD); + if (!tdma->is_virtualized) + tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD); + if (!tdma->global_cmd) goto clk_disable; @@ -777,7 +788,9 @@ static int __maybe_unused tegra_adma_runtime_resume(struct device *dev) dev_err(dev, "ahub clk_enable failed: %d\n", ret); return ret; } - tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); + + if (!tdma->is_virtualized) + tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); if (!tdma->global_cmd) return 0; @@ -846,6 +859,8 @@ static int tegra_adma_probe(struct platform_device *pdev) { const struct tegra_adma_chip_data *cdata; struct tegra_adma *tdma; + unsigned int ch_base_offset; + struct resource *res; int ret, i; cdata = of_device_get_match_data(&pdev->dev); @@ -865,9 +880,22 @@ static int tegra_adma_probe(struct platform_device *pdev) tdma->nr_channels = cdata->nr_channels; platform_set_drvdata(pdev, tdma); - tdma->base_addr = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(tdma->base_addr)) - return PTR_ERR(tdma->base_addr); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm"); + if (res) { + tdma->base_addr = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(tdma->base_addr)) + return PTR_ERR(tdma->base_addr); + + tdma->is_virtualized = true; + ch_base_offset = 0; + } else { + tdma->base_addr = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tdma->base_addr)) + return PTR_ERR(tdma->base_addr); + + tdma->is_virtualized = false; + ch_base_offset = cdata->ch_base_offset; + } tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio"); if (IS_ERR(tdma->ahub_clk)) { @@ -900,7 +928,7 @@ static int tegra_adma_probe(struct platform_device *pdev) if (!test_bit(i, tdma->dma_chan_mask)) continue; - tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset + tdc->chan_addr = tdma->base_addr + ch_base_offset + (cdata->ch_reg_size * i); tdc->irq = of_irq_get(pdev->dev.of_node, i);