| Message ID | 20241031165835.55065-1-marex@denx.de (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | dmaengine: xilinx_dma: Fix freeup active list based on descriptor completion bit | expand |
> -----Original Message----- > From: Marek Vasut <marex@denx.de> > Sent: Thursday, October 31, 2024 10:28 PM > To: dmaengine@vger.kernel.org > Cc: Marek Vasut <marex@denx.de>; Uwe Kleine-König <u.kleine- > koenig@baylibre.com>; Simek, Michal <michal.simek@amd.com>; Peter Korsgaard > <peter@korsgaard.com>; Pandey, Radhey Shyam > <radhey.shyam.pandey@amd.com>; Vinod Koul <vkoul@kernel.org>; linux-arm- > kernel@lists.infradead.org > Subject: [PATCH] dmaengine: xilinx_dma: Fix freeup active list based on descriptor > completion bit > > The xilinx_dma is completely broken since the referenced commit, > because if the (seg->hw.status & XILINX_DMA_BD_COMP_MASK) is not > set for whatever reason, the current descriptor is never moved to I want to understand more on this failure scenario. How to replicate it? Why is completion bit not set ? Based on the documentation completed bit indicates to the software that the DMA Engine has completed the transfer as described by the associated descriptor. The DMA Engine sets this bit to 1 when the transfer is completed. > the done list, and the DMA stops moving data. > > Isolate the newly added check to DMA which does implement irq_delay, > that way the new check is matching what is likely some new bit in a > new core, without breaking the DMA for older versions of the same > core. > > Fixes: 7bcdaa658102 ("dmaengine: xilinx_dma: Freeup active list based on > descriptor completion bit") > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: "Uwe Kleine-König" <u.kleine-koenig@baylibre.com> > Cc: Michal Simek <michal.simek@amd.com> > Cc: Peter Korsgaard <peter@korsgaard.com> > Cc: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > Cc: Vinod Koul <vkoul@kernel.org> > Cc: dmaengine@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > --- > drivers/dma/xilinx/xilinx_dma.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c > index 1bdd57de87a6e..48647c8a64a5b 100644 > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -1718,7 +1718,8 @@ static void xilinx_dma_complete_descriptor(struct > xilinx_dma_chan *chan) > return; > > list_for_each_entry_safe(desc, next, &chan->active_list, node) { > - if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { > + if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA > && > + chan->irq_delay) { > struct xilinx_axidma_tx_segment *seg; > > seg = list_last_entry(&desc->segments, > -- > 2.45.2
On 11/6/24 10:48 AM, Pandey, Radhey Shyam wrote: >> -----Original Message----- >> From: Marek Vasut <marex@denx.de> >> Sent: Thursday, October 31, 2024 10:28 PM >> To: dmaengine@vger.kernel.org >> Cc: Marek Vasut <marex@denx.de>; Uwe Kleine-König <u.kleine- >> koenig@baylibre.com>; Simek, Michal <michal.simek@amd.com>; Peter Korsgaard >> <peter@korsgaard.com>; Pandey, Radhey Shyam >> <radhey.shyam.pandey@amd.com>; Vinod Koul <vkoul@kernel.org>; linux-arm- >> kernel@lists.infradead.org >> Subject: [PATCH] dmaengine: xilinx_dma: Fix freeup active list based on descriptor >> completion bit >> >> The xilinx_dma is completely broken since the referenced commit, >> because if the (seg->hw.status & XILINX_DMA_BD_COMP_MASK) is not >> set for whatever reason, the current descriptor is never moved to > > I want to understand more on this failure scenario. How to replicate it? The very basic test is to use AXI DMA for DMA transfer, which fails to complete because of this new chunk of code. By reading the commit history, I can only conclude this was something that got added due to the irq_delay, but was never tested on core without irq_delay support ? > Why is completion bit not set ? Based on the documentation completed bit > indicates to the software that the DMA Engine has completed the transfer > as described by the associated descriptor. The DMA Engine sets this bit > to 1 when the transfer is completed. I don't know, the bit was not used before you added the bit and check of the bit in the problematic commit 7bcdaa658102 ("dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit")
> -----Original Message----- > From: Marek Vasut <marex@denx.de> > Sent: Wednesday, November 6, 2024 5:12 PM > To: Pandey, Radhey Shyam <radhey.shyam.pandey@amd.com>; > dmaengine@vger.kernel.org > Cc: Uwe Kleine-König <u.kleine-koenig@baylibre.com>; Simek, Michal > <michal.simek@amd.com>; Peter Korsgaard <peter@korsgaard.com>; Vinod Koul > <vkoul@kernel.org>; linux-arm-kernel@lists.infradead.org; Katakam, Harini > <harini.katakam@amd.com> > Subject: Re: [PATCH] dmaengine: xilinx_dma: Fix freeup active list based on > descriptor completion bit > > On 11/6/24 10:48 AM, Pandey, Radhey Shyam wrote: > >> -----Original Message----- > >> From: Marek Vasut <marex@denx.de> > >> Sent: Thursday, October 31, 2024 10:28 PM > >> To: dmaengine@vger.kernel.org > >> Cc: Marek Vasut <marex@denx.de>; Uwe Kleine-König <u.kleine- > >> koenig@baylibre.com>; Simek, Michal <michal.simek@amd.com>; Peter > >> Korsgaard <peter@korsgaard.com>; Pandey, Radhey Shyam > >> <radhey.shyam.pandey@amd.com>; Vinod Koul <vkoul@kernel.org>; > >> linux-arm- kernel@lists.infradead.org > >> Subject: [PATCH] dmaengine: xilinx_dma: Fix freeup active list based > >> on descriptor completion bit > >> > >> The xilinx_dma is completely broken since the referenced commit, > >> because if the (seg->hw.status & XILINX_DMA_BD_COMP_MASK) is not set > >> for whatever reason, the current descriptor is never moved to > > > > I want to understand more on this failure scenario. How to replicate it? > > The very basic test is to use AXI DMA for DMA transfer, which fails to complete > because of this new chunk of code. By reading the commit history, I can only > conclude this was something that got added due to the irq_delay, but was never > tested on core without irq_delay support ? This commit is also present in downstream xilinx kernel and all legacy regression are working fine without xlnx,irq-delay. Added Abin to this thread who confirmed that axidmatest client[1] works without IRQ delay. [1]: https://github.com/Xilinx/linux-xlnx/blob/master/drivers/dma/xilinx/axidmatest.c So I want to understand what is the test client you are using? > > > Why is completion bit not set ? Based on the documentation completed > > bit indicates to the software that the DMA Engine has completed the > > transfer as described by the associated descriptor. The DMA Engine > > sets this bit to 1 when the transfer is completed. > I don't know, the bit was not used before you added the bit and check of the bit in the > problematic commit 7bcdaa658102 ("dmaengine: xilinx_dma: > Freeup active list based on descriptor completion bit")
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 1bdd57de87a6e..48647c8a64a5b 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1718,7 +1718,8 @@ static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan) return; list_for_each_entry_safe(desc, next, &chan->active_list, node) { - if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { + if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA && + chan->irq_delay) { struct xilinx_axidma_tx_segment *seg; seg = list_last_entry(&desc->segments,
The xilinx_dma is completely broken since the referenced commit, because if the (seg->hw.status & XILINX_DMA_BD_COMP_MASK) is not set for whatever reason, the current descriptor is never moved to the done list, and the DMA stops moving data. Isolate the newly added check to DMA which does implement irq_delay, that way the new check is matching what is likely some new bit in a new core, without breaking the DMA for older versions of the same core. Fixes: 7bcdaa658102 ("dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit") Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: "Uwe Kleine-König" <u.kleine-koenig@baylibre.com> Cc: Michal Simek <michal.simek@amd.com> Cc: Peter Korsgaard <peter@korsgaard.com> Cc: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org --- drivers/dma/xilinx/xilinx_dma.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)