From patchwork Mon Dec 17 17:19:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Pimentel X-Patchwork-Id: 10734055 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B0CAE1850 for ; Mon, 17 Dec 2018 17:19:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A2C612A110 for ; Mon, 17 Dec 2018 17:19:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 965342A121; Mon, 17 Dec 2018 17:19:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AAD542A123 for ; Mon, 17 Dec 2018 17:19:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387846AbeLQRTs (ORCPT ); Mon, 17 Dec 2018 12:19:48 -0500 Received: from smtprelay4.synopsys.com ([198.182.47.9]:56488 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726763AbeLQRTs (ORCPT ); Mon, 17 Dec 2018 12:19:48 -0500 Received: from mailhost.synopsys.com (mailhost2.synopsys.com [10.13.184.66]) by smtprelay.synopsys.com (Postfix) with ESMTP id AD1DA24E27BF; Mon, 17 Dec 2018 09:19:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1545067187; bh=yE0kiemeZyK9Wus1jsnQceJSo2Q8hJGPaMdx4MBDxnA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:In-Reply-To: References:From; b=U3mtaQH04Wp6GPHQkOesx/kRFkjCdiAXBzQCP0xsMRlJbOO1+wmJ5dEaeiCYqs9Bf EmYaSj70xsL2vEShskZ7CTAPz6+nXRThvDPaexIvjW91OIC5m6hTy0utmxzr/ibv5w WfpZf6Z9PAj80acJBahu1pGbeLLKUJE+B13O0KsIWd2N5yZrDeux1GFES8yr718pcl N+KER20gCohBQo0+N+TdY58m83IPnfNIt/UzhgU3UA+G5VacGh2LL/aLrbt73PHQZ4 MlJzpBHFqR1Uw4YnRRhX4HIiFXB7V01HZ/irTKHaCub4giTKq/XhtXggvqwjFGsMn6 /fdOAlxoYY5KA== Received: from de02.synopsys.com (germany.internal.synopsys.com [10.225.17.21]) by mailhost.synopsys.com (Postfix) with ESMTP id 648F84039; Mon, 17 Dec 2018 09:19:47 -0800 (PST) Received: from de02dwia024.internal.synopsys.com (de02dwia024.internal.synopsys.com [10.225.19.81]) by de02.synopsys.com (Postfix) with ESMTP id 8D7527F39; Mon, 17 Dec 2018 18:19:45 +0100 (CET) From: Gustavo Pimentel To: linux-pci@vger.kernel.org, dmaengine@vger.kernel.org Cc: Gustavo Pimentel , Vinod Koul , Dan Williams , Eugeniy Paltsev , Andy Shevchenko , Russell King , Niklas Cassel , Lorenzo Pieralisi , Joao Pinto , Jose Abreu , Luis Oliveira , Vitor Soares , Nelson Costa , Pedro Sousa Subject: [RFC v2 5/6] dmaengine: Add Synopsys eDMA IP PCIe glue-logic Date: Mon, 17 Dec 2018 18:19:37 +0100 Message-Id: <8f7832bd6a32310019d2d01c8a2fa24cd0863d73.1545066805.git.gustavo.pimentel@synopsys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Synopsys eDMA IP is normally distributed along with Synopsys PCIe EndPoint IP (depends of the use and licensing agreement). This IP requires some basic configurations, such as: - eDMA registers BAR - eDMA registers offset - eDMA linked list BAR - eDMA linked list offset - eDMA linked list size - eDMA version - eDMA mode As a working example, PCIe glue-logic will attach to a Synopsys PCIe EndPoint IP prototype kit (Vendor ID = 0x16c3, Device ID = 0xedda), which has built-in an eDMA IP with this default configuration: - eDMA registers BAR = 0 - eDMA registers offset = 0x1000 (4 Kbytes) - eDMA linked list BAR = 2 - eDMA linked list offset = 0x0 (0 Kbytes) - eDMA linked list size = 0x20000 (128 Kbytes) - eDMA version = 0 - eDMA mode = EDMA_MODE_UNROLL This driver can be compile as built-in or external module in kernel. To enable this driver just select DW_EDMA_PCIE option in kernel configuration, however it requires and selects automatically DW_EDMA option too. Changes: RFC v1->RFC v2: - Replace comments // (C99 style) by /**/ - Merge two pcim_iomap_regions() calls into just one call - Remove pci_try_set_mwi() call - Replace some dev_info() by dev_dbg() to reduce *noise* - Remove pci_name(pdev) call after being call dw_edma_remove() - Remove all power management support - Fix the headers of the .c and .h files according to the most recent convention - Fix errors and checks pointed out by checkpatch with --strict option - Replace patch small description tag from dma by dmaengine Signed-off-by: Gustavo Pimentel Cc: Vinod Koul Cc: Dan Williams Cc: Eugeniy Paltsev Cc: Andy Shevchenko Cc: Russell King Cc: Niklas Cassel Cc: Lorenzo Pieralisi Cc: Joao Pinto Cc: Jose Abreu Cc: Luis Oliveira Cc: Vitor Soares Cc: Nelson Costa Cc: Pedro Sousa --- drivers/dma/dw-edma/Kconfig | 9 ++ drivers/dma/dw-edma/Makefile | 1 + drivers/dma/dw-edma/dw-edma-pcie.c | 258 +++++++++++++++++++++++++++++++++++++ 3 files changed, 268 insertions(+) create mode 100644 drivers/dma/dw-edma/dw-edma-pcie.c diff --git a/drivers/dma/dw-edma/Kconfig b/drivers/dma/dw-edma/Kconfig index 3016bed..c0838ce 100644 --- a/drivers/dma/dw-edma/Kconfig +++ b/drivers/dma/dw-edma/Kconfig @@ -7,3 +7,12 @@ config DW_EDMA help Support the Synopsys DesignWare eDMA controller, normally implemented on endpoints SoCs. + +config DW_EDMA_PCIE + tristate "Synopsys DesignWare eDMA PCIe driver" + depends on PCI && PCI_MSI + select DW_EDMA + help + Provides a glue-logic between the Synopsys DesignWare + eDMA controller and an endpoint PCIe device. This also serves + as a reference design to whom desires to use this IP. diff --git a/drivers/dma/dw-edma/Makefile b/drivers/dma/dw-edma/Makefile index 0c53033..8d45c0d 100644 --- a/drivers/dma/dw-edma/Makefile +++ b/drivers/dma/dw-edma/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_DW_EDMA) += dw-edma.o dw-edma-$(CONFIG_DEBUG_FS) := dw-edma-v0-debugfs.o dw-edma-objs := dw-edma-core.o \ dw-edma-v0-core.o $(dw-edma-y) +obj-$(CONFIG_DW_EDMA_PCIE) += dw-edma-pcie.o diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c new file mode 100644 index 0000000..6305768 --- /dev/null +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates. + * Synopsys DesignWare eDMA PCIe driver + */ + +#include +#include +#include +#include +#include + +#include "dw-edma-core.h" + +enum dw_edma_pcie_bar { + BAR_0, + BAR_1, + BAR_2, + BAR_3, + BAR_4, + BAR_5 +}; + +struct dw_edma_pcie_data { + enum dw_edma_pcie_bar regs_bar; + u64 regs_off; + enum dw_edma_pcie_bar ll_bar; + u64 ll_off; + size_t ll_sz; + u32 version; + enum dw_edma_mode mode; +}; + +static const struct dw_edma_pcie_data snps_edda_data = { + /* eDMA registers location */ + .regs_bar = BAR_0, + .regs_off = 0x1000, /* 4 KBytes */ + /* eDMA memory linked list location */ + .ll_bar = BAR_2, + .ll_off = 0, /* 0 KBytes */ + .ll_sz = 0x20000, /* 128 KBytes */ + /* Other */ + .version = 0, + .mode = EDMA_MODE_UNROLL, +}; + +static int dw_edma_pcie_probe(struct pci_dev *pdev, + const struct pci_device_id *pid) +{ + const struct dw_edma_pcie_data *pdata = (void *)pid->driver_data; + struct device *dev = &pdev->dev; + struct dw_edma_chip *chip; + struct dw_edma *dw; + void __iomem *reg; + int err, irq = -1; + u32 addr_hi, addr_lo; + u16 flags; + u8 cap_off; + + if (!pdata) { + dev_err(dev, "%s missing data struture\n", + pci_name(pdev)); + return -EFAULT; + } + + err = pcim_enable_device(pdev); + if (err) { + dev_err(dev, "%s enabling device failed\n", + pci_name(pdev)); + return err; + } + + err = pcim_iomap_regions(pdev, + BIT(pdata->regs_bar) | BIT(pdata->ll_bar), + pci_name(pdev)); + if (err) { + dev_err(dev, "%s eDMA BAR I/O remapping failed\n", + pci_name(pdev)); + return err; + } + + pci_set_master(pdev); + + err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + if (err) { + dev_err(dev, "%s DMA mask set failed\n", + pci_name(pdev)); + return err; + } + + err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); + if (err) { + dev_err(dev, "%s consistent DMA mask set failed\n", + pci_name(pdev)); + return err; + } + + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL); + if (!dw) + return -ENOMEM; + + irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX); + if (irq < 0) { + dev_err(dev, "%s failed to alloc IRQ vector\n", + pci_name(pdev)); + return -EPERM; + } + + chip->dw = dw; + chip->dev = dev; + chip->id = pdev->devfn; + chip->irq = pdev->irq; + + dw->regs = pcim_iomap_table(pdev)[pdata->regs_bar]; + dw->regs += pdata->regs_off; + + dw->va_ll = pcim_iomap_table(pdev)[pdata->ll_bar]; + dw->va_ll += pdata->ll_off; + dw->pa_ll = pdev->resource[pdata->ll_bar].start; + dw->pa_ll += pdata->ll_off; + dw->ll_sz = pdata->ll_sz; + + dw->msi_addr = 0; + dw->msi_data = 0; + + dw->version = pdata->version; + dw->mode = pdata->mode; + + dev_dbg(dev, "Version:\t%u\n", dw->version); + + dev_dbg(dev, "Mode:\t%s\n", + dw->mode == EDMA_MODE_LEGACY ? "Legacy" : "Unroll"); + + dev_dbg(dev, "Registers:\tBAR=%u, off=0x%.16llx B, addr=0x%.8lx\n", + pdata->regs_bar, pdata->regs_off, + (unsigned long)dw->regs); + + dev_dbg(dev, "L. List:\tBAR=%u, off=0x%.16llx B, sz=0x%.8x B, vaddr=0x%.8lx, paddr=0x%.8lx", + pdata->ll_bar, pdata->ll_off, pdata->ll_sz, + (unsigned long)dw->va_ll, + (unsigned long)dw->pa_ll); + + if (pdev->msi_cap && pdev->msi_enabled) { + cap_off = pdev->msi_cap + PCI_MSI_FLAGS; + pci_read_config_word(pdev, cap_off, &flags); + if (flags & PCI_MSI_FLAGS_ENABLE) { + cap_off = pdev->msi_cap + PCI_MSI_ADDRESS_LO; + pci_read_config_dword(pdev, cap_off, &addr_lo); + + if (flags & PCI_MSI_FLAGS_64BIT) { + cap_off = pdev->msi_cap + PCI_MSI_ADDRESS_HI; + pci_read_config_dword(pdev, cap_off, &addr_hi); + cap_off = pdev->msi_cap + PCI_MSI_DATA_64; + } else { + addr_hi = 0; + cap_off = pdev->msi_cap + PCI_MSI_DATA_32; + } + + dw->msi_addr = addr_hi; + dw->msi_addr <<= 32; + dw->msi_addr |= addr_lo; + + pci_read_config_dword(pdev, cap_off, &dw->msi_data); + dw->msi_data &= 0xffff; + + dev_dbg(dev, "MSI:\t\taddr=0x%.16llx, data=0x%.8x, nr=%d\n", + dw->msi_addr, dw->msi_data, pdev->irq); + } + } + + if (pdev->msix_cap && pdev->msix_enabled) { + u32 offset; + u8 bir; + + cap_off = pdev->msix_cap + PCI_MSIX_FLAGS; + pci_read_config_word(pdev, cap_off, &flags); + + if (flags & PCI_MSIX_FLAGS_ENABLE) { + cap_off = pdev->msix_cap + PCI_MSIX_TABLE; + pci_read_config_dword(pdev, cap_off, &offset); + + bir = offset & PCI_MSIX_TABLE_BIR; + offset &= PCI_MSIX_TABLE_OFFSET; + + reg = pcim_iomap_table(pdev)[bir]; + reg += offset; + + addr_lo = readl(reg + PCI_MSIX_ENTRY_LOWER_ADDR); + addr_hi = readl(reg + PCI_MSIX_ENTRY_UPPER_ADDR); + dw->msi_addr = addr_hi; + dw->msi_addr <<= 32; + dw->msi_addr |= addr_lo; + + dw->msi_data = readl(reg + PCI_MSIX_ENTRY_DATA); + + dev_dbg(dev, + "MSI-X:\taddr=0x%.16llx, data=0x%.8x, nr=%d\n", + dw->msi_addr, dw->msi_data, pdev->irq); + } + } + + if (!pdev->msi_enabled && !pdev->msix_enabled) { + dev_err(dev, "%s enable interrupt failed\n", + pci_name(pdev)); + return -EPERM; + } + + err = dw_edma_probe(chip); + if (err) { + dev_err(dev, "%s eDMA probe failed\n", + pci_name(pdev)); + return err; + } + + pci_set_drvdata(pdev, chip); + + dev_info(dev, "DesignWare eDMA PCIe driver loaded completely\n"); + + return 0; +} + +static void dw_edma_pcie_remove(struct pci_dev *pdev) +{ + struct dw_edma_chip *chip = pci_get_drvdata(pdev); + struct device *dev = &pdev->dev; + int err; + + err = dw_edma_remove(chip); + if (err) + dev_warn(dev, "can't remove device properly: %d\n", err); + + pci_free_irq_vectors(pdev); + + dev_info(dev, "DesignWare eDMA PCIe driver unloaded completely\n"); +} + +static const struct pci_device_id dw_edma_pcie_id_table[] = { + { PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) }, + { } +}; +MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table); + +static struct pci_driver dw_edma_pcie_driver = { + .name = "dw-edma-pcie", + .id_table = dw_edma_pcie_id_table, + .probe = dw_edma_pcie_probe, + .remove = dw_edma_pcie_remove, +}; + +module_pci_driver(dw_edma_pcie_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Synopsys DesignWare eDMA PCIe driver"); +MODULE_AUTHOR("Gustavo Pimentel ");