From patchwork Tue Oct 29 12:33:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 3107901 X-Patchwork-Delegate: vinod.koul@intel.com Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1938F9F2B7 for ; Tue, 29 Oct 2013 12:33:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EEA372022A for ; Tue, 29 Oct 2013 12:33:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CE98520216 for ; Tue, 29 Oct 2013 12:33:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754851Ab3J2Mde (ORCPT ); Tue, 29 Oct 2013 08:33:34 -0400 Received: from co1ehsobe001.messaging.microsoft.com ([216.32.180.184]:45766 "EHLO co1outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752620Ab3J2Md2 (ORCPT ); Tue, 29 Oct 2013 08:33:28 -0400 Received: from mail213-co1-R.bigfish.com (10.243.78.240) by CO1EHSOBE032.bigfish.com (10.243.66.97) with Microsoft SMTP Server id 14.1.225.22; Tue, 29 Oct 2013 12:33:28 +0000 Received: from mail213-co1 (localhost [127.0.0.1]) by mail213-co1-R.bigfish.com (Postfix) with ESMTP id 6467AD8011C; Tue, 29 Oct 2013 12:33:28 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6h1082kzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h2218h2216h1155h) Received: from mail213-co1 (localhost.localdomain [127.0.0.1]) by mail213-co1 (MessageSwitch) id 138305000595287_32387; Tue, 29 Oct 2013 12:33:25 +0000 (UTC) Received: from CO1EHSMHS024.bigfish.com (unknown [10.243.78.247]) by mail213-co1.bigfish.com (Postfix) with ESMTP id 07E3B4C0041; Tue, 29 Oct 2013 12:33:25 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO1EHSMHS024.bigfish.com (10.243.66.34) with Microsoft SMTP Server (TLS) id 14.16.227.3; Tue, 29 Oct 2013 12:33:24 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.3.158.2; Tue, 29 Oct 2013 12:33:23 +0000 Received: from rio.ap.freescale.net (rio.ap.freescale.net [10.192.242.9]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r9TCXCdx030074; Tue, 29 Oct 2013 05:33:19 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , Subject: [PATCH 1/3] dma: imx-sdma: Add ssi dual fifo script support Date: Tue, 29 Oct 2013 20:33:15 +0800 Message-ID: <9ed025d4e98f716ba80b27acaaa98f43ad3bd75a.1383047327.git.b42378@freescale.com> X-Mailer: git-send-email 1.8.4 In-Reply-To: References: MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There's a script for SSI missing in current sdma script list. Thus add it. This script would allow SSI use its dual fifo mode to transimit/receive data without occasional hardware underrun/overrun. This patch also fixed a counting error for total number of scripts. Signed-off-by: Nicolin Chen Acked-by: Kumar Gala --- Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt | 1 + drivers/dma/imx-sdma.c | 6 +++++- include/linux/platform_data/dma-imx-sdma.h | 2 ++ include/linux/platform_data/dma-imx.h | 1 + 4 files changed, 9 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt index 4fa814d..3b933c5 100644 --- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt @@ -42,6 +42,7 @@ The full ID of peripheral types can be found below. 19 IPU Memory 20 ASRC 21 ESAI + 22 SSI Dual FIFO The third cell specifies the transfer priority as below. diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index fc43603..695871f 100644 --- a/drivers/dma/imx-sdma.c +++ b/drivers/dma/imx-sdma.c @@ -724,6 +724,10 @@ static void sdma_get_pc(struct sdma_channel *sdmac, per_2_emi = sdma->script_addrs->app_2_mcu_addr; emi_2_per = sdma->script_addrs->mcu_2_app_addr; break; + case IMX_DMATYPE_SSI_DUAL: + per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; + emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; + break; case IMX_DMATYPE_SSI_SP: case IMX_DMATYPE_MMC: case IMX_DMATYPE_SDHC: @@ -1237,7 +1241,7 @@ static void sdma_issue_pending(struct dma_chan *chan) sdma_enable_channel(sdma, sdmac->channel); } -#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 +#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 37 static void sdma_add_scripts(struct sdma_engine *sdma, const struct sdma_script_start_addrs *addr) diff --git a/include/linux/platform_data/dma-imx-sdma.h b/include/linux/platform_data/dma-imx-sdma.h index 3a39428..19cfa9a 100644 --- a/include/linux/platform_data/dma-imx-sdma.h +++ b/include/linux/platform_data/dma-imx-sdma.h @@ -43,6 +43,8 @@ struct sdma_script_start_addrs { s32 dptc_dvfs_addr; s32 utra_addr; s32 ram_code_start_addr; + s32 mcu_2_ssish_addr; + s32 ssish_2_mcu_addr; }; /** diff --git a/include/linux/platform_data/dma-imx.h b/include/linux/platform_data/dma-imx.h index beac6b8..bcbc6c3 100644 --- a/include/linux/platform_data/dma-imx.h +++ b/include/linux/platform_data/dma-imx.h @@ -39,6 +39,7 @@ enum sdma_peripheral_type { IMX_DMATYPE_IPU_MEMORY, /* IPU Memory */ IMX_DMATYPE_ASRC, /* ASRC */ IMX_DMATYPE_ESAI, /* ESAI */ + IMX_DMATYPE_SSI_DUAL, /* SSI Dual FIFO */ }; enum imx_dma_prio {