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Mon, 18 Mar 2024 06:39:23 +0000 Received: from IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::8615:efe2:7c8e:2041]) by IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::8615:efe2:7c8e:2041%3]) with mapi id 15.20.7386.025; Mon, 18 Mar 2024 06:39:22 +0000 From: Inochi Amaoto To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Jisheng Zhang , Liu Gui , Jingbao Qiu , dlan@gentoo.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v4 4/4] dmaengine: add driver for Sophgo CV18XX/SG200X dmamux Date: Mon, 18 Mar 2024 14:38:51 +0800 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: X-TMN: [7qm0FjB5asIBI6vetYBPR8kdaSYNsdCZLJ2EnNQRv48=] X-ClientProxiedBy: TYCP301CA0074.JPNP301.PROD.OUTLOOK.COM (2603:1096:405:7d::14) To IA1PR20MB4953.namprd20.prod.outlook.com (2603:10b6:208:3af::19) X-Microsoft-Original-Message-ID: <20240318063852.1554712-4-inochiama@outlook.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR20MB4953:EE_|SN7PR20MB5460:EE_ X-MS-Office365-Filtering-Correlation-Id: 82558cd3-549a-4900-3413-08dc471625ab X-MS-Exchange-SLBlob-MailProps: 7J/vb0KDx3g6a7F03Qev6MOuCGwUNmfERvbL1B87uliY8ZRwG+wrIeHDOAedME1pjkGmrqmMix19l4z8NMY1kudSPJ7pYxqgCOYE7K42q0R8uhar0Xx7UstHHfBk+IHw44HwLe10w35cM19YJA94itnn+udRNbi9E6bqCbB0dvVc7xojYoYMTQvRvhnbtuiae6+kcOhi6IQDDKEHhbDzfCm6cftV3sIPU+dQYLVPR+MVAR1sAJHVc6FEFwASCA8Gn6EQDCgO0dPT1+O9bol8QwWy7BMuEeKX3f5bknzWPKMJie66WwjeYSIEUjMiZGUMPYF8rjVAPQFaHGJBCD9oh8/sSMxV/CnKaRhKpxPdGD0dCUNEKHbtkNJwWz0+nKLms0SDS/LB43rRHKEPZgY6LjBS2E3kAsHcFRJccbVNdPIPhGBEdYW10KNaODyZKMegwStMCQ+mUoMX2Y7WH1hHCmOnXHAiwjdwqGWtVVHYuApvQW++jRrpTbM85OcO6sBR01xIbo2jTm17Muce/eDOujZUVxKfmO2TSFlcYAtgon7sIqnvJIB7sZYkrvNLa7cFg8rw/FVNcdZVqLMfHBDvQSPz3vbrpe9vPELAwABGIaHX5JpvfAGrOuNxtVF0mdHoidHCgnQW0rcgQkcjZcWOtbL/cBCH6rD4yloH0WCFhvllBYlM7knBJM8VX6yBQhLiOqrhQKkrTF2Sb6i0qJvZYUYINRdHuyrLKps9zNl4m0hTSDHrrmLuZYCgSX72tn9thyJ5PSfJMo/Z5QGObmWiQx39lcwxEk7v/Q7qGEYAnR8= X-Microsoft-Antispam: BCL:0; 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The multiplexer supports at most 8 request lines. Add driver for Sophgo CV18XX/SG200X DMA multiplexer. Signed-off-by: Inochi Amaoto --- drivers/dma/Kconfig | 9 ++ drivers/dma/Makefile | 1 + drivers/dma/cv1800-dmamux.c | 232 ++++++++++++++++++++++++++++++++++++ 3 files changed, 242 insertions(+) create mode 100644 drivers/dma/cv1800-dmamux.c -- 2.44.0 diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 002a5ec80620..cb31520b9f86 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -546,6 +546,15 @@ config PLX_DMA These are exposed via extra functions on the switch's upstream port. Each function exposes one DMA channel. +config SOPHGO_CV1800_DMAMUX + tristate "Sophgo CV1800/SG2000 series SoC DMA multiplexer support" + depends on MFD_SYSCON + depends on ARCH_SOPHGO + help + Support for the DMA multiplexer on Sophgo CV1800/SG2000 + series SoCs. + Say Y here if your board have this soc. + config STE_DMA40 bool "ST-Ericsson DMA40 support" depends on ARCH_U8500 diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index dfd40d14e408..7465f249ee47 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/ obj-$(CONFIG_PXA_DMA) += pxa_dma.o obj-$(CONFIG_RENESAS_DMA) += sh/ obj-$(CONFIG_SF_PDMA) += sf-pdma/ +obj-$(CONFIG_SOPHGO_CV1800_DMAMUX) += cv1800-dmamux.o obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o obj-$(CONFIG_STM32_DMA) += stm32-dma.o obj-$(CONFIG_STM32_DMAMUX) += stm32-dmamux.o diff --git a/drivers/dma/cv1800-dmamux.c b/drivers/dma/cv1800-dmamux.c new file mode 100644 index 000000000000..b41c39f2e338 --- /dev/null +++ b/drivers/dma/cv1800-dmamux.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Inochi Amaoto + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DMAMUX_NCELLS 3 +#define MAX_DMA_MAPPING_ID DMA_SPI_NOR1 +#define MAX_DMA_CPU_ID DMA_CPU_C906_1 +#define MAX_DMA_CH_ID 7 + +#define DMAMUX_INTMUX_REGISTER_LEN 4 +#define DMAMUX_NR_CH_PER_REGISTER 4 +#define DMAMUX_BIT_PER_CH 8 +#define DMAMUX_CH_MASk GENMASK(5, 0) +#define DMAMUX_INT_BIT_PER_CPU 10 +#define DMAMUX_CH_UPDATE_BIT BIT(31) + +#define DMAMUX_CH_SET(chid, val) \ + (((val) << ((chid) * DMAMUX_BIT_PER_CH)) | DMAMUX_CH_UPDATE_BIT) +#define DMAMUX_CH_MASK(chid) \ + DMAMUX_CH_SET(chid, DMAMUX_CH_MASk) + +#define DMAMUX_INT_BIT(chid, cpuid) \ + BIT((cpuid) * DMAMUX_INT_BIT_PER_CPU + (chid)) +#define DMAMUX_INTEN_BIT(cpuid) \ + DMAMUX_INT_BIT(8, cpuid) +#define DMAMUX_INT_CH_BIT(chid, cpuid) \ + (DMAMUX_INT_BIT(chid, cpuid) | DMAMUX_INTEN_BIT(cpuid)) +#define DMAMUX_INT_MASK(chid) \ + (DMAMUX_INT_BIT(chid, DMA_CPU_A53) | \ + DMAMUX_INT_BIT(chid, DMA_CPU_C906_0) | \ + DMAMUX_INT_BIT(chid, DMA_CPU_C906_1)) +#define DMAMUX_INT_CH_MASK(chid, cpuid) \ + (DMAMUX_INT_MASK(chid) | DMAMUX_INTEN_BIT(cpuid)) + +struct cv1800_dmamux_data { + struct dma_router dmarouter; + struct regmap *regmap; + spinlock_t lock; + DECLARE_BITMAP(used_chans, MAX_DMA_CH_ID); + DECLARE_BITMAP(mapped_peripherals, MAX_DMA_MAPPING_ID); +}; + +struct cv1800_dmamux_map { + unsigned int channel; + unsigned int peripheral; + unsigned int cpu; +}; + +static void cv1800_dmamux_free(struct device *dev, void *route_data) +{ + struct cv1800_dmamux_data *dmamux = dev_get_drvdata(dev); + struct cv1800_dmamux_map *map = route_data; + u32 regoff = map->channel % DMAMUX_NR_CH_PER_REGISTER; + u32 regpos = map->channel / DMAMUX_NR_CH_PER_REGISTER; + unsigned long flags; + + spin_lock_irqsave(&dmamux->lock, flags); + + regmap_update_bits(dmamux->regmap, + regpos + CV1800_SDMA_DMA_CHANNEL_REMAP0, + DMAMUX_CH_MASK(regoff), + DMAMUX_CH_UPDATE_BIT); + + regmap_update_bits(dmamux->regmap, CV1800_SDMA_DMA_INT_MUX, + DMAMUX_INT_CH_MASK(map->channel, map->cpu), + DMAMUX_INTEN_BIT(map->cpu)); + + clear_bit(map->channel, dmamux->used_chans); + clear_bit(map->peripheral, dmamux->mapped_peripherals); + + spin_unlock_irqrestore(&dmamux->lock, flags); + + kfree(map); +} + +static void *cv1800_dmamux_route_allocate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); + struct cv1800_dmamux_data *dmamux = platform_get_drvdata(pdev); + struct cv1800_dmamux_map *map; + unsigned long flags; + unsigned int chid, devid, cpuid; + u32 regoff, regpos; + + if (dma_spec->args_count != DMAMUX_NCELLS) { + dev_err(&pdev->dev, "invalid number of dma mux args\n"); + return ERR_PTR(-EINVAL); + } + + chid = dma_spec->args[0]; + devid = dma_spec->args[1]; + cpuid = dma_spec->args[2]; + dma_spec->args_count -= 2; + + if (chid > MAX_DMA_CH_ID) { + dev_err(&pdev->dev, "invalid channel id: %u\n", chid); + return ERR_PTR(-EINVAL); + } + + if (devid > MAX_DMA_MAPPING_ID) { + dev_err(&pdev->dev, "invalid device id: %u\n", devid); + return ERR_PTR(-EINVAL); + } + + if (cpuid > MAX_DMA_CPU_ID) { + dev_err(&pdev->dev, "invalid cpu id: %u\n", cpuid); + return ERR_PTR(-EINVAL); + } + + dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", 0); + if (!dma_spec->np) { + dev_err(&pdev->dev, "can't get dma master\n"); + return ERR_PTR(-EINVAL); + } + + map = kzalloc(sizeof(*map), GFP_KERNEL); + if (!map) + return ERR_PTR(-ENOMEM); + + map->channel = chid; + map->peripheral = devid; + map->cpu = cpuid; + + regoff = chid % DMAMUX_NR_CH_PER_REGISTER; + regpos = chid / DMAMUX_NR_CH_PER_REGISTER; + + spin_lock_irqsave(&dmamux->lock, flags); + + if (test_and_set_bit(devid, dmamux->mapped_peripherals)) { + dev_err(&pdev->dev, "already used device mapping: %u\n", devid); + goto failed; + } + + if (test_and_set_bit(chid, dmamux->used_chans)) { + clear_bit(devid, dmamux->mapped_peripherals); + dev_err(&pdev->dev, "already used channel id: %u\n", chid); + goto failed; + } + + regmap_set_bits(dmamux->regmap, + regpos + CV1800_SDMA_DMA_CHANNEL_REMAP0, + DMAMUX_CH_SET(regoff, devid)); + + regmap_update_bits(dmamux->regmap, CV1800_SDMA_DMA_INT_MUX, + DMAMUX_INT_CH_MASK(chid, cpuid), + DMAMUX_INT_CH_BIT(chid, cpuid)); + + spin_unlock_irqrestore(&dmamux->lock, flags); + + dev_info(&pdev->dev, "register channel %u for req %u (cpu %u)\n", + chid, devid, cpuid); + + return map; + +failed: + spin_unlock_irqrestore(&dmamux->lock, flags); + dev_err(&pdev->dev, "already used channel id: %u\n", chid); + return ERR_PTR(-EBUSY); +} + +static int cv1800_dmamux_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *mux_node = dev->of_node; + struct cv1800_dmamux_data *data; + struct device *parent = dev->parent; + struct device_node *dma_master; + struct regmap *map = NULL; + + if (!parent) + return -ENODEV; + + map = device_node_to_regmap(parent->of_node); + if (IS_ERR(map)) + return PTR_ERR(map); + + dma_master = of_parse_phandle(mux_node, "dma-masters", 0); + if (!dma_master) { + dev_err(dev, "invalid dma-requests property\n"); + return -ENODEV; + } + of_node_put(dma_master); + + data = devm_kmalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + spin_lock_init(&data->lock); + data->regmap = map; + data->dmarouter.dev = dev; + data->dmarouter.route_free = cv1800_dmamux_free; + + platform_set_drvdata(pdev, data); + + return of_dma_router_register(mux_node, + cv1800_dmamux_route_allocate, + &data->dmarouter); +} + +static const struct of_device_id cv1800_dmamux_ids[] = { + { .compatible = "sophgo,cv1800-dmamux", }, + { } +}; +MODULE_DEVICE_TABLE(of, cv1800_dmamux_ids); + +static struct platform_driver cv1800_dmamux_driver = { + .driver = { + .name = "fsl-raideng", + .of_match_table = cv1800_dmamux_ids, + }, + .probe = cv1800_dmamux_probe, +}; +module_platform_driver(cv1800_dmamux_driver); + +MODULE_AUTHOR("Inochi Amaoto "); +MODULE_DESCRIPTION("Sophgo CV1800/SG2000 Series Soc DMAMUX driver"); +MODULE_LICENSE("GPL");