[v3,05/15] dmaengine: dw-edma: Add PCIe VSEC data retrieval support

Message ID	b775207eb60662486dd8ddd4cb2acb7173be7129.1612374941.git.gustavo.pimentel@synopsys.com (mailing list archive)
State	Changes Requested
Headers	show Return-Path: <dmaengine-owner@kernel.org> From: Gustavo Pimentel <Gustavo.Pimentel@synopsys.com> To: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, Vinod Koul <vkoul@kernel.org>, Dan Williams <dan.j.williams@intel.com>, Bjorn Helgaas <bhelgaas@google.com>, Gustavo Pimentel <Gustavo.Pimentel@synopsys.com> Subject: [PATCH v3 05/15] dmaengine: dw-edma: Add PCIe VSEC data retrieval support Date: Wed, 3 Feb 2021 18:56:57 +0100 Message-Id: <b775207eb60662486dd8ddd4cb2acb7173be7129.1612374941.git.gustavo.pimentel@synopsys.com> In-Reply-To: <cover.1612374941.git.gustavo.pimentel@synopsys.com> References: <cover.1612374941.git.gustavo.pimentel@synopsys.com> In-Reply-To: <cover.1612374941.git.gustavo.pimentel@synopsys.com> References: <cover.1612374941.git.gustavo.pimentel@synopsys.com> Precedence: bulk
Series	dmaengine: dw-edma: HDMA support \| expand [v3,00/15] dmaengine: dw-edma: HDMA support [v3,01/15] dmaengine: dw-edma: Add writeq() and readq() for 64 bits architectures [v3,02/15] dmaengine: dw-edma: Fix comments offset characters' alignment [v3,03/15] dmaengine: dw-edma: Add support for the HDMA feature [v3,04/15] PCI: Add pci_find_vsec_capability() to find a specific VSEC [v3,05/15] dmaengine: dw-edma: Add PCIe VSEC data retrieval support [v3,06/15] dmaengine: dw-edma: Add device_prep_interleave_dma() support [v3,07/15] dmaengine: dw-edma: Improve number of channels check [v3,08/15] dmaengine: dw-edma: Reorder variables to keep consistency [v3,09/15] dmaengine: dw-edma: Improve the linked list and data blocks definition [v3,10/15] dmaengine: dw-edma: Change linked list and data blocks offset and sizes [v3,11/15] dmaengine: dw-edma: Move struct dentry variable from static definition into dw_edma stru… [v3,12/15] dmaengine: dw-edma: Fix crash on loading/unloading driver [v3,13/15] dmaengine: dw-edma: Change DMA abreviation from lower into upper case [v3,14/15] dmaengine: dw-edma: Revert fix scatter-gather address calculation [v3,15/15] dmaengine: dw-edma: Add pcim_iomap_table return checker

diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index b971505..b65c32e1 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -863,15 +863,19 @@ int dw_edma_probe(struct dw_edma_chip *chip) raw_spin_lock_init(&dw->lock); - /* Find out how many write channels are supported by hardware */ - dw->wr_ch_cnt = dw_edma_v0_core_ch_count(dw, EDMA_DIR_WRITE); - if (!dw->wr_ch_cnt) - return -EINVAL; + if (!dw->wr_ch_cnt) { + /* Find out how many write channels are supported by hardware */ + dw->wr_ch_cnt = dw_edma_v0_core_ch_count(dw, EDMA_DIR_WRITE); + if (!dw->wr_ch_cnt) + return -EINVAL; + } - /* Find out how many read channels are supported by hardware */ - dw->rd_ch_cnt = dw_edma_v0_core_ch_count(dw, EDMA_DIR_READ); - if (!dw->rd_ch_cnt) - return -EINVAL; + if (!dw->rd_ch_cnt) { + /* Find out how many read channels are supported by hardware */ + dw->rd_ch_cnt = dw_edma_v0_core_ch_count(dw, EDMA_DIR_READ); + if (!dw->rd_ch_cnt) + return -EINVAL; + } dev_vdbg(dev, "Channels:\twrite=%d, read=%d\n", dw->wr_ch_cnt, dw->rd_ch_cnt); diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c index c130549..7077d79 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -13,9 +13,16 @@ #include <linux/dma/edma.h> #include <linux/pci-epf.h> #include <linux/msi.h> +#include <linux/bitfield.h> #include "dw-edma-core.h" +#define DW_PCIE_VSEC_DMA_ID 0x6 +#define DW_PCIE_VSEC_DMA_BAR GENMASK(10, 8) +#define DW_PCIE_VSEC_DMA_MAP GENMASK(2, 0) +#define DW_PCIE_VSEC_DMA_RD_CH GENMASK(25, 16) +#define DW_PCIE_VSEC_DMA_WR_CH GENMASK(9, 0) + struct dw_edma_pcie_data { /* eDMA registers location */ enum pci_barno rg_bar; @@ -32,6 +39,8 @@ struct dw_edma_pcie_data { /* Other */ enum dw_edma_map_format mf; u8 irqs; + u16 rd_ch_cnt; + u16 wr_ch_cnt; }; static const struct dw_edma_pcie_data snps_edda_data = { @@ -50,6 +59,8 @@ static const struct dw_edma_pcie_data snps_edda_data = { /* Other */ .mf = EDMA_MF_EDMA_UNROLL, .irqs = 1, + .rd_ch_cnt = 0, + .wr_ch_cnt = 0, }; static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr) @@ -61,10 +72,49 @@ static const struct dw_edma_core_ops dw_edma_pcie_core_ops = { .irq_vector = dw_edma_pcie_irq_vector, }; +static void dw_edma_pcie_get_vsec_dma_data(struct pci_dev *pdev, + struct dw_edma_pcie_data *pdata) +{ + u32 val, map; + u16 vsec; + u64 off; + + vsec = pci_find_vsec_capability(pdev, DW_PCIE_VSEC_DMA_ID); + if (!vsec) + return; + + pci_read_config_dword(pdev, vsec + PCI_VSEC_HEADER, &val); + if (PCI_VSEC_CAP_REV(val) != 0x00 || PCI_VSEC_CAP_LEN(val) != 0x18) + return; + + pci_dbg(pdev, "Detected PCIe Vendor-Specific Extended Capability DMA\n"); + pci_read_config_dword(pdev, vsec + 0x8, &val); + map = FIELD_GET(DW_PCIE_VSEC_DMA_MAP, val); + if (map != EDMA_MF_EDMA_LEGACY && + map != EDMA_MF_EDMA_UNROLL && + map != EDMA_MF_HDMA_COMPAT) + return; + + pdata->mf = map; + pdata->rg_bar = FIELD_GET(DW_PCIE_VSEC_DMA_BAR, val); + + pci_read_config_dword(pdev, vsec + 0xc, &val); + pdata->rd_ch_cnt = FIELD_GET(DW_PCIE_VSEC_DMA_RD_CH, val); + pdata->wr_ch_cnt = FIELD_GET(DW_PCIE_VSEC_DMA_WR_CH, val); + + pci_read_config_dword(pdev, vsec + 0x14, &val); + off = val; + pci_read_config_dword(pdev, vsec + 0x10, &val); + off <<= 32; + off |= val; + pdata->rg_off = off; +} + static int dw_edma_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *pid) { - const struct dw_edma_pcie_data *pdata = (void *)pid->driver_data; + struct dw_edma_pcie_data *pdata = (void *)pid->driver_data; + struct dw_edma_pcie_data vsec_data; struct device *dev = &pdev->dev; struct dw_edma_chip *chip; struct dw_edma *dw; @@ -77,10 +127,18 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return err; } + memcpy(&vsec_data, pdata, sizeof(struct dw_edma_pcie_data)); + + /* + * Tries to find if exists a PCIe Vendor-Specific Extended Capability + * for the DMA, if exists one, then reconfigures with the new data + */ + dw_edma_pcie_get_vsec_dma_data(pdev, &vsec_data); + /* Mapping PCI BAR regions */ - err = pcim_iomap_regions(pdev, BIT(pdata->rg_bar) | - BIT(pdata->ll_bar) | - BIT(pdata->dt_bar), + err = pcim_iomap_regions(pdev, BIT(vsec_data.rg_bar) | + BIT(vsec_data.ll_bar) | + BIT(vsec_data.dt_bar), pci_name(pdev)); if (err) { pci_err(pdev, "eDMA BAR I/O remapping failed\n"); @@ -123,7 +181,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; /* IRQs allocation */ - nr_irqs = pci_alloc_irq_vectors(pdev, 1, pdata->irqs, + nr_irqs = pci_alloc_irq_vectors(pdev, 1, vsec_data.irqs, PCI_IRQ_MSI | PCI_IRQ_MSIX); if (nr_irqs < 1) { pci_err(pdev, "fail to alloc IRQ vector (number of IRQs=%u)\n", @@ -137,27 +195,29 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, chip->id = pdev->devfn; chip->irq = pdev->irq; - dw->rg_region.vaddr = pcim_iomap_table(pdev)[pdata->rg_bar]; - dw->rg_region.vaddr += pdata->rg_off; - dw->rg_region.paddr = pdev->resource[pdata->rg_bar].start; - dw->rg_region.paddr += pdata->rg_off; - dw->rg_region.sz = pdata->rg_sz; - - dw->ll_region.vaddr = pcim_iomap_table(pdev)[pdata->ll_bar]; - dw->ll_region.vaddr += pdata->ll_off; - dw->ll_region.paddr = pdev->resource[pdata->ll_bar].start; - dw->ll_region.paddr += pdata->ll_off; - dw->ll_region.sz = pdata->ll_sz; - - dw->dt_region.vaddr = pcim_iomap_table(pdev)[pdata->dt_bar]; - dw->dt_region.vaddr += pdata->dt_off; - dw->dt_region.paddr = pdev->resource[pdata->dt_bar].start; - dw->dt_region.paddr += pdata->dt_off; - dw->dt_region.sz = pdata->dt_sz; - - dw->mf = pdata->mf; + dw->rg_region.vaddr = pcim_iomap_table(pdev)[vsec_data.rg_bar]; + dw->rg_region.vaddr += vsec_data.rg_off; + dw->rg_region.paddr = pdev->resource[vsec_data.rg_bar].start; + dw->rg_region.paddr += vsec_data.rg_off; + dw->rg_region.sz = vsec_data.rg_sz; + + dw->ll_region.vaddr = pcim_iomap_table(pdev)[vsec_data.ll_bar]; + dw->ll_region.vaddr += vsec_data.ll_off; + dw->ll_region.paddr = pdev->resource[vsec_data.ll_bar].start; + dw->ll_region.paddr += vsec_data.ll_off; + dw->ll_region.sz = vsec_data.ll_sz; + + dw->dt_region.vaddr = pcim_iomap_table(pdev)[vsec_data.dt_bar]; + dw->dt_region.vaddr += vsec_data.dt_off; + dw->dt_region.paddr = pdev->resource[vsec_data.dt_bar].start; + dw->dt_region.paddr += vsec_data.dt_off; + dw->dt_region.sz = vsec_data.dt_sz; + + dw->mf = vsec_data.mf; dw->nr_irqs = nr_irqs; dw->ops = &dw_edma_pcie_core_ops; + dw->rd_ch_cnt = vsec_data.rd_ch_cnt; + dw->wr_ch_cnt = vsec_data.wr_ch_cnt; /* Debug info */ if (dw->mf == EDMA_MF_EDMA_LEGACY) @@ -170,15 +230,15 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, pci_dbg(pdev, "Version:\tUnknown (0x%x)\n", dw->mf); pci_dbg(pdev, "Registers:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", - pdata->rg_bar, pdata->rg_off, pdata->rg_sz, + vsec_data.rg_bar, vsec_data.rg_off, vsec_data.rg_sz, dw->rg_region.vaddr, &dw->rg_region.paddr); pci_dbg(pdev, "L. List:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", - pdata->ll_bar, pdata->ll_off, pdata->ll_sz, + vsec_data.ll_bar, vsec_data.ll_off, vsec_data.ll_sz, dw->ll_region.vaddr, &dw->ll_region.paddr); pci_dbg(pdev, "Data:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", - pdata->dt_bar, pdata->dt_off, pdata->dt_sz, + vsec_data.dt_bar, vsec_data.dt_off, vsec_data.dt_sz, dw->dt_region.vaddr, &dw->dt_region.paddr); pci_dbg(pdev, "Nr. IRQs:\t%u\n", dw->nr_irqs);

[v3,05/15] dmaengine: dw-edma: Add PCIe VSEC data retrieval support

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