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Tue, 25 Aug 2020 12:06:39 +0000 From: Yash Shah To: robh+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com Cc: aou@eecs.berkeley.edu, james.morse@arm.com, rrichter@marvell.com, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, sachin.ghadi@sifive.com, Yash Shah Subject: [PATCH 0/3] SiFive DDR controller and EDAC support Date: Tue, 25 Aug 2020 17:36:19 +0530 Message-Id: <1598357182-4226-1-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 2.7.4 X-ClientProxiedBy: BMXPR01CA0023.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:d::33) To BN6PR1301MB2020.namprd13.prod.outlook.com (2603:10b6:405:34::34) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from 255.255.255.255 (255.255.255.255) by BMXPR01CA0023.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:d::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3305.24 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: PfZ4cxIv+XUx6jwsJtewtIyynGYJ3HcF4u4RoEOYcj7A/akI1+UOs82OumQ/l3N1JVQa0+ySUyWA1SxVYHFKlazg116AlhPLKK+zglRRMoSZeDAPjEMvKzJIq49roCTizV0TdwoL12BjBP0BuGgIaMvTIbJ+L7UkEIC4kft5lM1fYTU2BVfnd+zRTg2aL63/s1EeLQj1NqNxsRw2yduVeO/9w7xuphaZkuvxnEG9GlZj4V2b/JCbDecma2GtqiZjsleod9LKDOyJy/Fy3j3kyeQKefIWvQ3lWzUQ5xvLwklYu+cVFS5DjpECPk5Pqf4GmC2gS32l358DYQsUxkmHLyc/xnDIFYV4V5CPCWKg43SFKj2nuQxPR1Dx6OCe7cEkKALDvodG3SpQ4yF6DzYlm/g+ovXFHtmG5aMqszOJGTwIr7k5DrFotqTk/dUJTS38J4OjAigGZHOU5KQMlSyvapDY5DlLJMk01HptLSQc/BSQdOxw2eY3vMFEg6FGaWuK/cZekSL8EZL0Qw/u9hkB3a0HIxRENz+RzxrIIYTR7Tr70gureWjjY9bsSh+lnSueiTp+DGdkIkOP6ZmPtRlO4UC6P7xeD8UFQMHIenpad2Iuy2KwMJRk8TigditxaeC8B5DIK+12kfo66XVJoFaNdQ== X-OriginatorOrg: sifive.com X-MS-Exchange-CrossTenant-Network-Message-Id: 393b4aa6-0c28-4ee0-5409-08d848ef5252 X-MS-Exchange-CrossTenant-AuthSource: BN6PR1301MB2020.namprd13.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Aug 2020 12:06:39.1754 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +KanYP9o44S5UlbKe5pWlQnJQViKn20gBt9WZstjw0aT+3MWkzCJdkA3fcLBD0U5BYtxbU2dkyMLwkmQ58YwKw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1301MB1873 Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The series add supports for SiFive DDR controller driver. This driver is use to manage the Cadence DDR controller present in SiFive SoCs. Currently it manages only the EDAC feature of the DDR controller. The series also adds Memory controller EDAC support for SiFive platform. It register for notifier event from SiFive DDR controller driver. The series is tested and based on Linux v5.8. For testing on Hifive Unleashed: 1. Enable the ECC bit of DDR controller during DDR initialization 2. Erase the entire DRAM in bootloader stage 3. Using FWC feature of DDR controller force ecc error to test Yash Shah (3): dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs soc: sifive: Add SiFive specific Cadence DDR controller driver edac: sifive: Add EDAC support for Memory Controller in SiFive SoCs .../devicetree/bindings/riscv/sifive-ddr.yaml | 41 ++++ drivers/edac/Kconfig | 2 +- drivers/edac/sifive_edac.c | 117 ++++++++++++ drivers/soc/sifive/Kconfig | 6 + drivers/soc/sifive/Makefile | 3 +- drivers/soc/sifive/sifive_ddr.c | 207 +++++++++++++++++++++ include/soc/sifive/sifive_ddr.h | 73 ++++++++ 7 files changed, 447 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/riscv/sifive-ddr.yaml create mode 100644 drivers/soc/sifive/sifive_ddr.c create mode 100644 include/soc/sifive/sifive_ddr.h