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Wed, 21 Aug 2019 23:59:54 +0000 From: "Ghannam, Yazen" To: "linux-edac@vger.kernel.org" CC: "Ghannam, Yazen" , "linux-kernel@vger.kernel.org" , "bp@alien8.de" Subject: [PATCH v3 0/8] AMD64 EDAC fixes Thread-Topic: [PATCH v3 0/8] AMD64 EDAC fixes Thread-Index: AQHVWHyGkq5ZZJpNOUKXQmjNKGyrbg== Date: Wed, 21 Aug 2019 23:59:53 +0000 Message-ID: <20190821235938.118710-1-Yazen.Ghannam@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN2PR01CA0006.prod.exchangelabs.com (2603:10b6:804:2::16) To SN6PR12MB2639.namprd12.prod.outlook.com (2603:10b6:805:6f::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Yazen.Ghannam@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e35ab55a-d07a-45c0-217b-08d72693a922 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:SN6PR12MB2815; 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There are also a couple of fixes for older issues. In addition, there are a couple of patches to add support for Asymmetric Dual-Rank DIMMs. I don't have the failing config readily available that you used, but I believe I found the issue. Please let me know how it goes. I've also added RFC patches to avoid the "ECC disabled" message for nodes without memory. I haven't fully tested these, but I wanted to get your thoughts. Here's an earlier discussion: https://lkml.kernel.org/r/20180321191335.7832-1-Yazen.Ghannam@amd.com Thanks, Yazen Link: https://lkml.kernel.org/r/20190709215643.171078-1-Yazen.Ghannam@amd.com v2->v3: * Drop Fixes: tags in patch 1. * Add detection of x8 DRAM devices in patches 2 and 3. * Fix Chip Select size printing in patch 4. * Added RFC patches to avoid "ECC disabled" message for nodes without memory. v1->v2: * Squash patches 1 and 2 together. Yazen Ghannam (10): EDAC/amd64: Support more than two controllers for chip selects handling EDAC/amd64: Recognize DRAM device type with EDAC_CTL_CAP EDAC/amd64: Initialize DIMM info for systems with more than two channels EDAC/amd64: Find Chip Select memory size using Address Mask EDAC/amd64: Decode syndrome before translating address EDAC/amd64: Cache secondary Chip Select registers EDAC/amd64: Support Asymmetric Dual-Rank DIMMs EDAC/amd64: Gather hardware information early EDAC/amd64: Use cached data when checking for ECC EDAC/amd64: Check for memory before fully initializing an instance drivers/edac/amd64_edac.c | 371 +++++++++++++++++++++++++------------- drivers/edac/amd64_edac.h | 9 +- 2 files changed, 251 insertions(+), 129 deletions(-)