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Fri, 24 Apr 2020 10:31:59 +0200 Received: from vleu-orange.cadence.com (localhost.localdomain [127.0.0.1]) by vleu-orange.cadence.com (8.14.4/8.14.4) with ESMTP id 03O8VxR1031006; Fri, 24 Apr 2020 10:31:59 +0200 Received: (from dkangude@localhost) by vleu-orange.cadence.com (8.14.4/8.14.4/Submit) id 03O8Vw5s031001; Fri, 24 Apr 2020 10:31:58 +0200 From: Dhananjay Kangude To: CC: , , , , , , , , Dhananjay Kangude Subject: [PATCH v4 0/2] Add EDAC support for Cadence ddr controller Date: Fri, 24 Apr 2020 10:31:53 +0200 Message-ID: <20200424083155.30918-1-dkangude@cadence.com> X-Mailer: git-send-email 2.15.0 MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:158.140.1.147;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:sjmaillnx1.cadence.com;PTR:unknown.Cadence.COM;CAT:NONE;SFTY:;SFS:(10009020)(4636009)(136003)(346002)(396003)(376002)(39860400002)(36092001)(46966005)(36756003)(5660300002)(336012)(47076004)(7636003)(86362001)(82740400003)(246002)(6916009)(426003)(6666004)(70586007)(36906005)(2906002)(8936002)(478600001)(82310400002)(42186006)(316002)(8676002)(70206006)(2616005)(26005)(54906003)(107886003)(186003)(4326008)(1076003)(356005);DIR:OUT;SFP:1101; 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Cadence controller detects single(CE) and double(UE) bit errors during memory operations(RMW). DDR controller raised the interrupt on detection of the ecc error event and fill the data into registers. Driver handle the interrupt event and notify edac subsystem about ecc errors. Changes since v4: ================= - Add Makefile change - Coreected YAML file fixes Changes since v3: ================= - Corrected YAML file location Changes since v2: ================= - Added minor fixes to YAML file - Split ISR into two differnt functions - Removed unused paramters - Fixed indentation issues - Improved code readabilty - Checked return value for edac_get_dimm - Modified quirks as a ip_features Changes since v1: ================= - Made predefined arrays as static Fixes: 201447a5db9b ("EDAC/Cadence:Add EDAC driver for cadence memory controller") - Replace macro 'EDAC_DIMM_PTR' with newly introduce function - Removed unused variable root*** SUBJECT HERE *** Dhananjay Kangude (2): dt-bindings: edac: Add cadence ddr mc support EDAC/Cadence:Add EDAC driver for cadence memory controller .../devicetree/bindings/edac/cdns,ddr-edac.yaml | 45 ++ drivers/edac/Kconfig | 8 + drivers/edac/Makefile | 1 + drivers/edac/cadence_edac.c | 641 ++++++++++++++++++++ 4 files changed, 695 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml create mode 100644 drivers/edac/cadence_edac.c