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Thu, 3 Sep 2020 20:01:48 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: Yazen Ghannam , linux-kernel@vger.kernel.org, tony.luck@intel.com, x86@kernel.org, Smita.KoralahalliChannabasappa@amd.com Subject: [PATCH v2 0/8] AMD MCA Address Translation Updates Date: Thu, 3 Sep 2020 20:01:36 +0000 Message-Id: <20200903200144.310991-1-Yazen.Ghannam@amd.com> X-Mailer: git-send-email 2.25.1 X-ClientProxiedBy: SN4PR0501CA0075.namprd05.prod.outlook.com (2603:10b6:803:22::13) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from 255.255.255.255 (255.255.255.255) by SN4PR0501CA0075.namprd05.prod.outlook.com (2603:10b6:803:22::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.7 via Frontend Transport; Thu, 3 Sep 2020 20:01:47 +0000 X-Mailer: git-send-email 2.25.1 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 53489b0c-6d45-4364-caab-08d8504430f4 X-MS-TrafficTypeDiagnostic: BN8PR12MB2980: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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Patches 1 & 3: Fixes an input to the address translation function. The translation requires a physical Die ID (NodeId in AMD documentation) rather than a logicial NUMA node ID. This is because the physical and logical nodes may not always match. Patch 2: Removes a function that is no longer needed with Patch 1. Patches 4-7: Code cleanup in preparation for Patch 8. Patch 8: Add translation support for new memory interleaving options available in Rome systems. The patch is based on the latest AMD reference code for the address translation. Patches 6-8 have checkpatch warnings about long lines, but I kept the long lines for readability. Thanks, Yazen Link: https://lkml.kernel.org/r/20200814191449.183998-1-Yazen.Ghannam@amd.com v1 -> v2: * Save the AMD NodeId value in struct cpuinfo_x86 rather than use a local value in MCA code. * Include code cleanup for AMD MCA Address Translation function before adding new functionality. Muralidhara M K (1): x86/MCE/AMD Support new memory interleaving modes during address translation Yazen Ghannam (7): x86/CPU/AMD: Save NodeId on AMD-based systems x86/CPU/AMD: Remove amd_get_nb_id() EDAC/mce_amd: Use struct cpuinfo_x86.node_id for NodeId x86/MCE/AMD: Use defines for register addresses in translation code x86/MCE/AMD: Use macros to get bitfields in translation code x86/MCE/AMD: Drop tmp variable in translation code x86/MCE/AMD: Group register reads in translation code arch/x86/events/amd/core.c | 2 +- arch/x86/include/asm/cacheinfo.h | 4 +- arch/x86/include/asm/processor.h | 3 +- arch/x86/kernel/amd_nb.c | 4 +- arch/x86/kernel/cpu/amd.c | 17 +- arch/x86/kernel/cpu/cacheinfo.c | 8 +- arch/x86/kernel/cpu/hygon.c | 11 +- arch/x86/kernel/cpu/mce/amd.c | 284 ++++++++++++++++++++++--------- arch/x86/kernel/cpu/mce/inject.c | 4 +- drivers/edac/amd64_edac.c | 4 +- drivers/edac/mce_amd.c | 4 +- 11 files changed, 233 insertions(+), 112 deletions(-)