[v3,0/1] Add L1 and L2 error detection for A53 and A57

Message

Sascha Hauer Jan. 7, 2021, 10:38 a.m. UTC

Hi all,

It's been a while since I last sent this, so here's an update.

Like Rob suggested I dropped using a virtual device tree node
to attach the driver to, so from the original three patches series
is only one patch left now. I think I have integrated all review
feedback I got last time, please have a look.

One thing that I find unfortunate in the driver is that I have to
register the "cpu" hierarchy under edac for all CPUs. Only the
CPUs supported by this driver actually count anything. On JUNO for
example we have four cortex-a53 cores (which are supported by this
driver) and four cortex-a72 cores (which are not supported).
Nevertheless we create the directory hierarchy for all eight cores.
I don't know how I should work around this, but maybe James has an
idea.

As usual, feedback welcome.

Sascha

Changes since v2:
- drop usage of virtual dt node (Robh)
- use read_sysreg_s instead of open coded variant (James Morse)
- separate error retrieving from error reporting
- use smp_call_function_single rather than smp_call_function_single_async
- make driver single instance and register all 'cpu' hierarchy up front once

Changes since v1:
- Split dt-binding into separate patch
- Sort local function variables in reverse-xmas tree order
- drop unnecessary comparison and make variable bool

Sascha Hauer (1):
  drivers/edac: Add L1 and L2 error detection for A53 and A57

 drivers/edac/Kconfig              |   6 +
 drivers/edac/Makefile             |   1 +
 drivers/edac/cortex_arm64_l1_l2.c | 218 ++++++++++++++++++++++++++++++
 3 files changed, 225 insertions(+)
 create mode 100644 drivers/edac/cortex_arm64_l1_l2.c