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Thu, 28 Oct 2021 17:57:53 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT006.mail.protection.outlook.com (10.13.174.246) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4649.14 via Frontend Transport; Thu, 28 Oct 2021 17:57:53 +0000 Received: from yaz-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Thu, 28 Oct 2021 12:57:49 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , Yazen Ghannam , Subject: [PATCH v3 00/33] AMD MCA Address Translation Updates Date: Thu, 28 Oct 2021 17:56:55 +0000 Message-ID: <20211028175728.121452-1-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 91b7edd6-ce29-45f2-9863-08d99a3c7708 X-MS-TrafficTypeDiagnostic: BY5PR12MB4872: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:57:53.3754 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 91b7edd6-ce29-45f2-9863-08d99a3c7708 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4872 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org This patchset refactors the AMD MCA Address Translation code and adds support for newer systems. The reference code was recently refactored in preparation for updates for future systems. These patches try to follow the reference code as closely as possible. I also tried to address comments from previous patchset reviews. Patch 1 moves the address translation code from arch/x86 to EDAC. Patch 2 moves the df_indirect_read() function from arch/x86 to EDAC also, since this is used only by the address translation code. Patches 3-28 do the refactor without adding new system support. The goal is to break down the translation algorithm into smaller chunks. Code that changes between Data Fabric versions or interleaving modes is moved to a set of function pointers. The intention is that new system support can be added without any major refactor. I tried to make a patch for each logical change. The top level function was split first, then the next level of functions, etc. in a somewhat breadth-first approach. Patch 29 adds support for systems with Data Fabric version 3 (Rome and later). Patch 30 adds a short glossary for acronyms used in the translation code. Patches 31-32 prep for future systems including, but not limited to, heterogeneous CPU+GPU systems. Patch 33 adds support for systems with Data Fabric version 3.5 (heterogeneous CPU+GPU systems). Each patch was build tested individually. The entire set was functionally tested with the following modes. Naples: No interleaving Channel interleaving Die interleaving Socket interleaving Rome: No interleaving Nodes-per-Socket 0 (NPS0) Nodes-per-Socket 1 (NPS1) Nodes-per-Socket 2 (NPS2) Nodes-per-Socket 4 (NPS4) NPS2 w/o hashing NPS4 w/o hashing This version of the set was rebased on the following set. https://lkml.kernel.org/r/20211025145018.29985-1-nchatrad@amd.com I've copied x86@kernel.org for the cover letter and first two patches that touch arch/x86. The EDAC maintainers are copied for the whole set. Thanks, Yazen Cc: Link: https://lkml.kernel.org/r/20210623192002.3671647-1-yazen.ghannam@amd.com v2->v3: * Drop "df_regs" use. * Include patches needed for CPU+GPU systems. * Set "df_ops" at module init based on family type. v1->v2: * Move address translation code to EDAC. * Use function pointers to handle code differences between DF versions. * Add glossary of acronyms. Muralidhara M K (1): EDAC/amd64: Add address translation support for DF3.5 Yazen Ghannam (32): x86/MCE/AMD, EDAC/amd64: Move address translation to AMD64 EDAC x86/amd_nb, EDAC/amd64: Move DF Indirect Read to AMD64 EDAC EDAC/amd64: Allow for DF Indirect Broadcast reads EDAC/amd64: Add context struct EDAC/amd64: Define Data Fabric operations EDAC/amd64: Define functions for DramOffset EDAC/amd64: Define function to read DRAM address map registers EDAC/amd64: Define function to find interleaving mode EDAC/amd64: Define function to denormalize address EDAC/amd64: Define function to add DRAM base and hole EDAC/amd64: Define function to dehash address EDAC/amd64: Define function to check DRAM limit address EDAC/amd64: Remove goto statements EDAC/amd64: Simplify function parameters EDAC/amd64: Define function to get Interleave Address Bit EDAC/amd64: Skip denormalization if no interleaving EDAC/amd64: Define function to get number of interleaved channels EDAC/amd64: Define function to get number of interleaved dies EDAC/amd64: Define function to get number of interleaved sockets EDAC/amd64: Remove unnecessary assert EDAC/amd64: Define function to make space for CS ID EDAC/amd64: Define function to calculate CS ID EDAC/amd64: Define function to insert CS ID into address EDAC/amd64: Define function to get CS Fabric ID EDAC/amd64: Define function to find shift and mask values EDAC/amd64: Update CS ID calculation to match reference code EDAC/amd64: Match hash function to reference code EDAC/amd64: Define function to get interleave address select bit EDAC/amd64: Add support for address translation on DF3 systems EDAC/amd64: Add glossary of acronyms for address translation EDAC/amd64: Add check for when to add DRAM base and hole EDAC/amd64: Save the number of block instances arch/x86/include/asm/amd_nb.h | 1 - arch/x86/include/asm/mce.h | 3 - arch/x86/kernel/amd_nb.c | 49 +- arch/x86/kernel/cpu/mce/amd.c | 200 -------- drivers/edac/amd64_edac.c | 911 +++++++++++++++++++++++++++++++++- 5 files changed, 910 insertions(+), 254 deletions(-)