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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: g4bBv1oXKX17GHI21KZGqjZ00iEBz+7OuNtiM2QebsbJ0WXqd2slrR/tloonZdIOKW8yPM2AXoO36icQTrCbfRBDqQcd+Eew3XmJPX795+cxt7LKBZ4Dy/TIMIngsji40qYyVI1YdyLGqXs1W0d2DsBEecDkCpCxoCbf0jqKYcUTcg5nupCQoyRiRJLahZz+nCvOxJwu82R/DSo6EeADptak9Y2NG0Tm7NbXMh8xGISwfWV97ZBmovkgTc9LsN1iv56iA5kbqp9SSxqqcGFIa2qORNzYgy/uQrveZgeHyhX7NwAven5z//4ImXYNttiULFXwdk+GhV91yRtFAYOhK6onrPVJb1gedtvCr4wRrWPPkh8jZYhPoX2NdTAyut70JpgH/1MELKYaJNHxdrpvdKdmBGClY3+vJv3L3W/fahgalAuGyXMSKJ1nsITApPcY5V5oT0vbYxvnPdEyDMt9b8pgj2Bdc+tScM3CBka4e/WVODA3LubxoskZgxOEjArZ250iQa9xUl2OGelBf0g7O4BkeeQZpsuH2vZyCdiALvvrZhTewPGx2109HiHfHvbQA6VmhZMgexK0Pa3BUIvjdQADzWr7oClQhwK409kwAYdL7fJVBhQieaTGnC1tsHxjtpRXriXOH2SjQPH6jmxyN1RdsDFueseuT0PFyRSwxHCNGjQfZRDNQtBSqTx5d2eh5eSiX+GaCd/pngy384Cm4MsM6Isomajp2zkKQr7UT+ZJ2simwIpigonAZ/R+rcEoTxHKXWJ+EWWJtNp1SCIYP0doyE35/Wpck+D6IXr/+1K84wNh9WGJCTND/eggqW4rVyIGdE4ls6hwAXBgrdR5unO7wNcK6XYNEFB2TAakA08r0lWQDL21cfHB5zaLjswnL4AchuTeO18U9e83Jpsh+P9BDcy4rKRMF73VqwEKAa6qPTpRj9YpdeUMcOkPpU02A20duLt8o3osI3eydcjg7SDPa1873iZct8pjsyOtRtXL+NRtAkghwYw+J0L2NCzr939xYfOfLFrPFf7kulRD5+A2VTlIFtVg6ZgFitKDHTkBdok+2nDD4EVoN3G8iJDXuej3idN8WCEONmfkhiOyiZxfn/yiZjzjpOpm5Ggt0nBOEWKeJTMJv/4t1L2K6a/YsoolKzTLhWm5ffpRpkab4DGhOwpyAfUSgQtfDZ+2IxlR1rQJQn2WxH6iMU1k87BInQ6r1Dyf/Wy4jTFlKYPTU7hoMjopNWjd1UszpyoscSthAjJac/6qh+YLCkBgV1dUwxjtcJMUU95Wm7eyROnLOsJQifl5rm5ys44EqkEm/uFRPkaHtb4hjXUFConiqdBGP0pPh+2ANR8P5x4HvKa+JFsQJSE0gtO06uhNuSzpoom2EzQwTnibB6z6ZI7ERN+paS2mt1D3XGCuBl8AUAUONvd6Z/UoiB6sk2K1L8SoNj+WejiSzgGpDwvY9OsF1CRxdsIRGqISTWDMgbJbWw9kJdp1pCijk9E3sML4nRo/qJRFbUaZPDd/GRibfNFMZcKxTi36OMw3ypPI90FUx06HflN4hysrGz8YCKBwVpaj8st/DDa5TzSYQuWTb+S+fK3AECLlRUAagEOKER5oiFvXesh3NsRqW53EwLaGK+aOwIgkFhC5SLtamoXTT4fp+pfuUTPzrPiz4OgZp1oGCtuY/NpyUWCMIi02vQzYycAzHKWE3lVSTOhev2iuA+lkQZhjAPlgbsz8CIn2MXY+LbuvRQ== X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2ec46937-4874-4489-db75-08d9af6ce948 X-MS-Exchange-CrossTenant-AuthSource: CH0PR01MB7033.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Nov 2021 17:07:35.9450 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 5V/ZYq+BRZX5WnagWQQuLTolbxtvmY5d1AyCGHfA4OGp126fuye6xjpDA1GPj3W3ZL3VAgfDRwDM4Koimb+pSkOd2TW4/JZviKQA5A2XTo5GcXF+TA2hPYl/no84cOBF X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR01MB5654 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org This series adds support for the ARM Error Source Table (AEST) based on the latest version of ACPI for the Armv8 RAS Extensions [0]. The AEST driver supports both memory mapped and system register interfaces. This series assumes system register interfaces are only registered with private peripheral interrupts (PPIs); otherwise there is no guarantee the core handling the error is the core which took the error and has the syndrome info in it's system registers. This is meant to be initial support for AEST to address the current gaps with systems that support ARMv8 RAS extensions but don't have firmware-first support. This series simply logs all the errors it finds and triggers a kernel panic if there is an UE present. I have tested this series on Ampere Altra using processor errors to exercise PPI handling with system register interface and memory errors to exercise SPI handling with MMIO interface. Both corrected and uncorrected errors were tested to verify the non-fatal vs fatal scenarios. Future work: - UER handling to avoid panic - Looping through all external abort capable (ERRFR.UE != 0) error nodes in SEA/SEI handling Changes from RFC patch series [1]: - Updated for latest AEST spec - Utilize ACPICA header defines of AEST structures - Added support for ARMv8.4 RAS extension - Dropped the SEA/SEI dumping of SR RAS registers - Removed unused defines - Unified RAS extension register printing to a single function - Updated trace event with additional fields - Addressed other feedback from RFC series - Added myself to ARM64 ACPI MAINTAINERS as a reviewer [0] https://developer.arm.com/documentation/den0085/latest [1] https://lkml.org/lkml/2019/7/2/781 Tyler Baicar (2): ACPI/AEST: Initial AEST driver trace, ras: add ARM RAS extension trace event MAINTAINERS | 1 + arch/arm64/include/asm/ras.h | 52 ++++ arch/arm64/include/asm/sysreg.h | 2 + arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/ras.c | 129 +++++++++ arch/arm64/kvm/sys_regs.c | 2 + drivers/acpi/arm64/Kconfig | 3 + drivers/acpi/arm64/Makefile | 1 + drivers/acpi/arm64/aest.c | 455 ++++++++++++++++++++++++++++++++ include/linux/acpi_aest.h | 50 ++++ include/linux/cpuhotplug.h | 1 + include/ras/ras_event.h | 55 ++++ 12 files changed, 752 insertions(+) create mode 100644 arch/arm64/include/asm/ras.h create mode 100644 arch/arm64/kernel/ras.c create mode 100644 drivers/acpi/arm64/aest.c create mode 100644 include/linux/acpi_aest.h