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Peter Anvin" , "Dave Hansen" , Yazen Ghannam , Smita Koralahalli Subject: [RFC PATCH 0/2] Handle AMD threshold interrupt storms Date: Thu, 17 Feb 2022 08:16:07 -0600 Message-ID: <20220217141609.119453-1-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1865a77d-30af-4fd8-3482-08d9f2201303 X-MS-TrafficTypeDiagnostic: DM6PR12MB4185:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VbM+UEzCZD8oDDVuio8Zn151Zm8IFDDDCt1hKPIV/JreshrgxLOTejyuwKx6n7h0Jr6lnn182fhFZgqPPlntunoaVe1b5+wdjhvrNfw8QziSC33wCNUD7HRvvi2p3MNyncewq0h2wqLKg0FiT50ky3ZtvzUTneuk/EA4AfEHU7O2geIGtQIcCfyQ3HraiQJJz8S17u7zjZxafQ0NsSpMCKUH6atLO+MlXSJpGHCSInPaLaNAMGFA58KU4UNcEpYUdza6spWULWU5IVczM7/R4rATItLAu9hp8/QLgmjRJ3cTZ60r9E8nXQeT6RXSWjK8SQYKrc5im1dYkZjCU2Jgik5Bsz8UDleLoyeUdrFkLD6QvI218XiqlGRq4tnTm61gcTtIPuTd89RKjso19pP/tHzQ/JDGPgEPrFxygXAcBHzNJ/EnntOhODMvLeVtwxe7lJzunq3JvPNET2lVnCNZm5t1OekmTzw5v1NorDWOg9cWzoaZ3t9Au74lp1uYXLzxW2paK6CZ3oN6EF4tnvUY/JYvHdXOiERynT1YxtJpOCXT5WR9Urz7pnxlEuxGzCSTsVwtU9CcX7fbPZmCVrD/xJk7kiYcUgIILVM/Y7OVz7wBcNi/jb6mvcXMlse0agMgOSSdJ+ywtwPBeqRqIBk1upyL5uOJznOGr+khSUcwXevXlNPVg9PMs8ChxmgupTdySWVSyALA2VEFrx4Nwkj5sQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(86362001)(110136005)(54906003)(47076005)(508600001)(6666004)(36860700001)(5660300002)(7696005)(316002)(426003)(4743002)(82310400004)(2906002)(336012)(8936002)(40460700003)(356005)(1076003)(70206006)(70586007)(16526019)(2616005)(26005)(186003)(4744005)(36756003)(83380400001)(8676002)(4326008)(81166007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Feb 2022 14:16:22.0863 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1865a77d-30af-4fd8-3482-08d9f2201303 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4185 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org This series of patches handles interrupt storms in AMD threshold interrupt handler. Patch 1 takes care of handling the storms and Patch 2 does some refactoring and simplification to reuse the existing function. Smita Koralahalli (2): x86/mce: Handle AMD threshold interrupt storms x86/mce: Simplify code in log_and_reset_block() arch/x86/kernel/cpu/mce/amd.c | 131 ++++++++++++++++++++++++++++- arch/x86/kernel/cpu/mce/core.c | 16 +++- arch/x86/kernel/cpu/mce/intel.c | 2 +- arch/x86/kernel/cpu/mce/internal.h | 8 +- 4 files changed, 148 insertions(+), 9 deletions(-)