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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0001709C.mail.protection.outlook.com (10.167.18.106) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8445.10 via Frontend Transport; Thu, 13 Feb 2025 16:46:23 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 13 Feb 2025 10:46:22 -0600 From: Yazen Ghannam Subject: [PATCH v2 00/16] AMD MCA interrupts rework Date: Thu, 13 Feb 2025 16:45:49 +0000 Message-ID: <20250213-wip-mca-updates-v2-0-3636547fe05f@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAL4hrmcC/x2OwRKCIBRFf8VhHQYkWq36j8bFE17KAmSALHP89 8Dlmbn33LuRiMFgJPdqIwEXE83sMohTRdQEbkRqdGYimJBMcEY/xlOrgL69hoSRDqgFtJ26Kdm R3PIBX+Z7GJ995gEi0iGAU1PxJOPPFmLCUMKTiWkO67G+8FIpQw2T4sKlbBteiyuTDeeU0xV+6 Ooxn3JgH2B1rWZL+n3f/0LlHtvFAAAA X-Change-ID: 20250210-wip-mca-updates-bed2a67c9c57 To: , Tony Luck CC: , , , Yazen Ghannam , X-Mailer: b4 0.15-dev-e27d6 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709C:EE_|CH3PR12MB9079:EE_ X-MS-Office365-Filtering-Correlation-Id: 045c96b2-5418-4cd7-7431-08dd4c4df368 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024|13003099007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2025 16:46:23.5286 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 045c96b2-5418-4cd7-7431-08dd4c4df368 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9079 Hi all, This set unifies the AMD MCA interrupt handlers with common MCA code. The goal is to avoid duplicating functionality like reading and clearing MCA banks. Based on feedback, this revision also include changes to the MCA init flow. Patches 1-4: General fixes and cleanups. Patches 5-10: Add BSP-only init flow and related changes. Patches 11-15: Updates from v1 set. Patch 16: Interrupt storm handling rebased on current set. Thanks, Yazen Tested-by: Tony Luck Reviewed-by: Tony Luck --- Changes in v2: - Add general cleanup pre-patches. - Add changes for BSP-only init. - Add interrupt storm handling for AMD. - Link to v1: https://lore.kernel.org/r/20240523155641.2805411-1-yazen.ghannam@amd.com --- Borislav Petkov (1): x86/mce: Cleanup bank processing on init Smita Koralahalli (1): x86/mce: Handle AMD threshold interrupt storms Yazen Ghannam (14): x86/mce: Don't remove sysfs if thresholding sysfs init fails x86/mce/amd: Remove return value for mce_threshold_create_device() x86/mce/amd: Remove smca_banks_map x86/mce/amd: Put list_head in threshold_bank x86/mce: Remove __mcheck_cpu_init_early() x86/mce: Define BSP-only init x86/mce: Define BSP-only SMCA init x86/mce: Do 'UNKNOWN' vendor check early x86/mce: Separate global and per-CPU quirks x86/mce: Move machine_check_poll() status checks to helper functions x86/mce: Unify AMD THR handler with MCA Polling x86/mce: Unify AMD DFR handler with MCA Polling x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems x86/mce/amd: Support SMCA Corrected Error Interrupt arch/x86/include/asm/mce.h | 7 +- arch/x86/kernel/cpu/common.c | 1 + arch/x86/kernel/cpu/mce/amd.c | 391 +++++++++++++----------------------- arch/x86/kernel/cpu/mce/core.c | 322 ++++++++++++++--------------- arch/x86/kernel/cpu/mce/intel.c | 15 ++ arch/x86/kernel/cpu/mce/internal.h | 8 + arch/x86/kernel/cpu/mce/threshold.c | 3 + 7 files changed, 332 insertions(+), 415 deletions(-) --- base-commit: b36de8b904b8ff2095ece7af6b3cfff8c73c2fb1 change-id: 20250210-wip-mca-updates-bed2a67c9c57