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[v3,00/17] AMD MCA interrupts rework

Message ID 20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com (mailing list archive)
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Series AMD MCA interrupts rework | expand

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Yazen Ghannam April 15, 2025, 2:54 p.m. UTC 
Hi all,

This set unifies the AMD MCA interrupt handlers with common MCA code.
The goal is to avoid duplicating functionality like reading and clearing
MCA banks.

Based on feedback, this revision also include changes to the MCA init
flow.

Patches 1-4:
General fixes and cleanups.

Patches 5-10:
Add BSP-only init flow and related changes.

Patches 11-15:
Updates from v1 set.

Patch 16:
Interrupt storm handling rebased on current set.

Patch 17:
Fix how poll settings are restored after a CMCI storm.

Thanks,
Yazen

---
Changes in v3:
- Rebased on tip/x86/merge rather than tip/master.
- Updated MSR access helpers (*msrl -> *msrq).
- Add patch to fix polling after a storm.
- Link to v2: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-0-3636547fe05f@amd.com

Changes in v2:
- Add general cleanup pre-patches.
- Add changes for BSP-only init.
- Add interrupt storm handling for AMD.
- Link to v1: https://lore.kernel.org/r/20240523155641.2805411-1-yazen.ghannam@amd.com

---
Borislav Petkov (1):
      x86/mce: Cleanup bank processing on init

Smita Koralahalli (1):
      x86/mce: Handle AMD threshold interrupt storms

Yazen Ghannam (15):
      x86/mce: Don't remove sysfs if thresholding sysfs init fails
      x86/mce/amd: Remove return value for mce_threshold_{create,remove}_device()
      x86/mce/amd: Remove smca_banks_map
      x86/mce/amd: Put list_head in threshold_bank
      x86/mce: Remove __mcheck_cpu_init_early()
      x86/mce: Define BSP-only init
      x86/mce: Define BSP-only SMCA init
      x86/mce: Do 'UNKNOWN' vendor check early
      x86/mce: Separate global and per-CPU quirks
      x86/mce: Move machine_check_poll() status checks to helper functions
      x86/mce: Unify AMD THR handler with MCA Polling
      x86/mce: Unify AMD DFR handler with MCA Polling
      x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems
      x86/mce/amd: Support SMCA Corrected Error Interrupt
      x86/mce: Restore poll settings after storm subsides

 arch/x86/include/asm/mce.h          |  11 +-
 arch/x86/kernel/cpu/common.c        |   1 +
 arch/x86/kernel/cpu/mce/amd.c       | 397 +++++++++++++-----------------------
 arch/x86/kernel/cpu/mce/core.c      | 331 +++++++++++++++---------------
 arch/x86/kernel/cpu/mce/intel.c     |  18 ++
 arch/x86/kernel/cpu/mce/internal.h  |  10 +
 arch/x86/kernel/cpu/mce/threshold.c |   3 +
 7 files changed, 347 insertions(+), 424 deletions(-)
---
base-commit: e6090e017e4b1e2a1e461750b7281a05f4e07a76
change-id: 20250210-wip-mca-updates-bed2a67c9c57