Show patches with: Submitter = Yash Shah       |    State = Action Required       |   10 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[3/3] EDAC/sifive: Add support for SiFive BEU in SiFive platform EDAC [1/3] dt-bindings: riscv: Add DT documentation for SiFive Bus Error Unit 1 - - --- 2020-11-12 Yash Shah New
[2/3] soc: sifive: beu: Add support for SiFive Bus Error Unit [1/3] dt-bindings: riscv: Add DT documentation for SiFive Bus Error Unit - - - --- 2020-11-12 Yash Shah New
[1/3] dt-bindings: riscv: Add DT documentation for SiFive Bus Error Unit [1/3] dt-bindings: riscv: Add DT documentation for SiFive Bus Error Unit - 1 - --- 2020-11-12 Yash Shah New
[v2,3/3] EDAC/sifive: Add EDAC support for Memory Controller in SiFive SoCs SiFive DDR controller and EDAC support 2 1 - --- 2020-09-07 Yash Shah New
[v2,2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver SiFive DDR controller and EDAC support 1 1 - --- 2020-09-07 Yash Shah New
[v2,1/3] dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs SiFive DDR controller and EDAC support 1 1 - --- 2020-09-07 Yash Shah New
[3/3] edac: sifive: Add EDAC support for Memory Controller in SiFive SoCs SiFive DDR controller and EDAC support 1 1 - --- 2020-08-25 Yash Shah New
[2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver SiFive DDR controller and EDAC support 1 1 - --- 2020-08-25 Yash Shah New
[1/3] dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs SiFive DDR controller and EDAC support 1 1 - --- 2020-08-25 Yash Shah New
riscv: move sifive_l2_cache.h to include/soc riscv: move sifive_l2_cache.h to include/soc - 2 - --- 2020-01-08 Yash Shah New