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Tue, 25 Aug 2020 12:06:50 +0000 From: Yash Shah To: robh+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com Cc: aou@eecs.berkeley.edu, james.morse@arm.com, rrichter@marvell.com, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, sachin.ghadi@sifive.com, Yash Shah Subject: [PATCH 1/3] dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs Date: Tue, 25 Aug 2020 17:36:20 +0530 Message-Id: <1598357182-4226-2-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598357182-4226-1-git-send-email-yash.shah@sifive.com> References: <1598357182-4226-1-git-send-email-yash.shah@sifive.com> X-ClientProxiedBy: BMXPR01CA0023.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:d::33) To BN6PR1301MB2020.namprd13.prod.outlook.com (2603:10b6:405:34::34) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from 255.255.255.255 (255.255.255.255) by BMXPR01CA0023.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:d::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3305.24 via Frontend Transport; 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Currently the driver is + used to manage EDAC feature of the DDR controller. + +maintainers: + - Yash Shah + +properties: + compatible: + enum: + - sifive,fu540-c000-ddr + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + memory-controller@100b0000 { + compatible = "sifive,fu540-c000-ddr"; + reg = <0x100b0000 0x4000>; + interrupts = <31>; + };