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Thu, 12 Nov 2020 12:01:24 +0000 From: Yash Shah To: robh+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, james.morse@arm.com, rric@kernel.org Cc: aou@eecs.berkeley.edu, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, sachin.ghadi@sifive.com, Yash Shah Subject: [PATCH 1/3] dt-bindings: riscv: Add DT documentation for SiFive Bus Error Unit Date: Thu, 12 Nov 2020 17:30:55 +0530 Message-Id: <1605182457-86046-1-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 2.7.4 X-Originating-IP: [159.117.144.156] X-ClientProxiedBy: BMXPR01CA0024.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:d::34) To BY5PR13MB4453.namprd13.prod.outlook.com (2603:10b6:a03:1d1::19) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from osubuntu003.open-silicon.com (159.117.144.156) by BMXPR01CA0024.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:d::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3541.21 via Frontend Transport; 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The + BEU can be configured to generate interrupts on correctable memory errors, + uncorrectable memory errors, and/or TileLink bus errors. + All the properties in ePAPR/DeviceTree specification applies for this platform. + +properties: + compatible: + items: + - const: sifive,fu740-c000-beu + - const: sifive,beu0 + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +additionalProperties: false + +required: + - compatible + - interrupts + - reg + +examples: + - | + bus-error-unit@1700000 { + compatible = "sifive,fu740-c000-beu", "sifive,beu0"; + reg = <0x1700000 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <65>; + };