| Message ID | 20201013125033.4749-2-s.hauer@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add L1 and L2 error detection for A53 and A57 | expand |
On Tue, 13 Oct 2020 14:50:31 +0200, Sascha Hauer wrote: > The ARM Cortex-A53 and A57 CPUs support error detection for the L1/L2 > caches. This patch adds a binding for the corresponding driver. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > .../bindings/edac/arm,cortex-a5x-edac.yaml | 32 +++++++++++++++++++ > 1 file changed, 32 insertions(+) > create mode 100644 Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml > My bot found errors running 'make dt_binding_check' on your patch: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml: 'maintainers' is a required property /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml: ignoring, error in schema: warning: no schema found in file: ./Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml See https://patchwork.ozlabs.org/patch/1381567 If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure dt-schema is up to date: pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade Please check and re-submit.
diff --git a/Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml b/Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml new file mode 100644 index 000000000000..de9325b688a0 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/arm,cortex-a5x-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM cortex A53/A57 EDAC bindings + +description: |+ + This contains the binding to support error detection for the L1 and L2 caches + on ARM Cortex A53 and A57 cores. + +properties: + compatible: + items: + - const: arm,cortex-a53-edac + - const: arm,cortex-a57-edac + + cpus: + minItems: 1 + description: phandles to the cpu nodes this device handles + +required: + - compatible + - cpus + +examples: + - | + edac-a53 { + compatible = "arm,cortex-a53-edac"; + cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; + };
The ARM Cortex-A53 and A57 CPUs support error detection for the L1/L2 caches. This patch adds a binding for the corresponding driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- .../bindings/edac/arm,cortex-a5x-edac.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml