diff mbox series

[3/3] arm64: dts: ls104x: Add L1/L2 cache edac node

Message ID 20201013125033.4749-4-s.hauer@pengutronix.de (mailing list archive)
State New, archived
Headers show
Series Add L1 and L2 error detection for A53 and A57 | expand

Commit Message

Sascha Hauer Oct. 13, 2020, 12:50 p.m. UTC 
From: York Sun <york.sun@nxp.com>

The Cortex A53/A57 cores on the Layerscape LS104x SoCs support EDAC
for the L1/L2 caches. Add the corresponding nodes for it.

Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 5 +++++
 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 5 +++++
 2 files changed, 10 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 5c2e370f6316..76cc62b02494 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -935,6 +935,11 @@  optee {
 		};
 	};
 
+	edac-a53 {
+		compatible = "arm,cortex-a53-edac";
+		cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
 };
 
 #include "qoriq-qman-portals.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 0246d975a206..ed35211c9b35 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -895,6 +895,11 @@  optee {
 			method = "smc";
 		};
 	};
+
+	edac-a57 {
+		compatible = "arm,cortex-a57-edac";
+		cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
 };
 
 #include "qoriq-qman-portals.dtsi"