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Fri, 7 May 2021 19:02:11 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: Yazen Ghannam , linux-kernel@vger.kernel.org, tony.luck@intel.com, x86@kernel.org, Smita.KoralahalliChannabasappa@amd.com Subject: [PATCH 18/25] x86/MCE/AMD: Define function to make space for CS ID Date: Fri, 7 May 2021 15:01:33 -0400 Message-Id: <20210507190140.18854-19-Yazen.Ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210507190140.18854-1-Yazen.Ghannam@amd.com> References: <20210507190140.18854-1-Yazen.Ghannam@amd.com> X-Originating-IP: [165.204.25.250] X-ClientProxiedBy: BN6PR21CA0010.namprd21.prod.outlook.com (2603:10b6:404:8e::20) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from aus-x-yghannam.amd.com (165.204.25.250) by BN6PR21CA0010.namprd21.prod.outlook.com (2603:10b6:404:8e::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4129.3 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: OjKBuoz6mw9V7xXNbIyAAq6kliP3HklEhLJihtp2XTxCXHBbDepBt1k9HME51vOcfkwXYeq9upO1SDY9cKdoRjR3VLwl+whPVSS33xVTawCmrKwbo0w0XHbpAgQepM6H9OR98aK7GJh0ajLSmNwcI/Emcb/uCierkgF0HZjrCOE7EAIxUJfjxYgh3j8xB7nerimyqgazHLv5x4wKK9iEsje+s5jvNOmFEdRkg8WP1xQuiBQQ3jWzgoglqwCmmHpkdDnT/guV4Q3ehxWfOHyQLYAZGl/39+RRjsQNtStk5aLoHJ1BUrq6XB1CiZHqyQpnqAGwPWxHAv/vYp3F5RLCZt6BtCTY8cPSbwTI0CrkSO3/3BCdT9ac3B7Qe1ldHuh7WTp9j5woElm1HKJZEryzG9tSMwfdNUgjITFlEaaZM5mMgUWkstEaby0DsnTjZItMqc6tnFpOVAVx4ZJxdUBnBhsvfMKIn2xKko0TIREnv7ph8gIIedRSnu1xEhbLafB5eLR60HWMdHZZy1b36FiIj2jSA6tJY/wRzj/Yb8blUwrBevpLccIojrayjt8C9776GOfUqpFN8vcXAFRNy+7UtycbWkCs32YDTyn1pbE6FvdXwnBVi6ruPLt/KuON3xerrb1MceDOaVej0/MAKeo4dCrLgvN4nZ4se1qeqD/Sng42mKzOF2zbs887AZzJ4OOqS5lBzalE541J3s2Vj8XdPrnmaU0+goWMdU5WaLs50P8U36zwiODfb3VSq38p7P9W1W5sI6XfauKIjzaURm1cscUZTjfnEoy64h56g/Uov9PNFKCwfmV8GUmYjgdug5jle+rnbO3Mu3AMgTwfzPXIpJhP5TFwRk/bN/GeNA9RaJeX4aEQb4EMDRmXTtEQb3ThWS1wtJzYJ6eVirYnnXkq0UVThiDgxI0yw21r2bBtVYS5IMGmv8NJfpD09A7CnHzbTqJ5xvBTTfvWdVK6hiz+1bLc3gn8sYWTxbUk9kMbBua93+4e2hl9hX3k4HCVk53v/2AZIu5aBByWJEzvhwuEbrYe8AHtGr5th8AaYbpdg8cqA083Rw0ZOUiMr/Pw3nixPtgYW2phNCIOdL5McvYC/UFUnwxp043ZLb3htC2zyhIF4e1SmxqkkML3O4cpQz1AUrtz7kLprJ0n4UJCifgRXIWIcDDNgD16n9tOHfSFbnY8UslKIbdfPY6z/cVhxDxREEaE2Jk1D/Exe5wvYKhTPpOoPPIHqfVRYj4MYDJkY2ipQVeu/oL2eWPMGE0a6iJk6G8tQktyQl3ggDb5e35Y22UYAdHg2CQ9knNclJszEByg0dkx6lV3K6uIgA24RaMa X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 84670962-b579-4e95-692f-08d9118a9e8f X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2021 19:02:11.5072 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: CZQWoUmA9L64rbb5P5wSJKe/z2W2Cf/rzzZC8ydQIJnZjF+83V139gDLYxuwbF8CRfmhMt4r7Iyijw1N1NcK9w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1620 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Yazen Ghannam Move code to makes a gap for the CS ID into a separate helper function. The exact bits to use vary based on interleaving mode. New interleaving modes in future DF versions will be added as new cases. Also, introduce a helper function that does the bit manipulation to make the gap. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 43 ++++++++++++++++++++++++++++------- 1 file changed, 35 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 8f4838a3d509..ba365901e39d 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -860,6 +860,38 @@ static void get_intlv_num_sockets(struct addr_ctx *ctx) ctx->intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; } +static void expand_bits(u8 start_bit, u8 num_bits, u64 *value) +{ + u64 temp1, temp2; + + if (start_bit == 0) { + *value <<= num_bits; + return; + } + + temp1 = *value & GENMASK_ULL(start_bit - 1, 0); + temp2 = (*value & GENMASK_ULL(63, start_bit)) << num_bits; + *value = temp1 | temp2; +} + +static void make_space_for_cs_id(struct addr_ctx *ctx) +{ + u8 num_intlv_bits; + + switch (ctx->intlv_mode) { + case NOHASH_2CH: + case DF2_HASH_2CH: + num_intlv_bits = ctx->intlv_num_chan; + num_intlv_bits += ctx->intlv_num_dies; + num_intlv_bits += ctx->intlv_num_sockets; + expand_bits(ctx->intlv_addr_bit, num_intlv_bits, &ctx->ret_addr); + break; + default: + /* Valid interleaving modes where checked earlier. */ + break; + } +} + static int denormalize_addr(struct addr_ctx *ctx) { u32 tmp; @@ -878,13 +910,11 @@ static int denormalize_addr(struct addr_ctx *ctx) get_intlv_num_dies(ctx); get_intlv_num_sockets(ctx); - num_intlv_bits = ctx->intlv_num_chan; - num_intlv_bits += ctx->intlv_num_dies; - num_intlv_bits += ctx->intlv_num_sockets; + make_space_for_cs_id(ctx); if (num_intlv_bits > 0) { - u64 temp_addr_x, temp_addr_i, temp_addr_y; u8 die_id_bit, sock_id_bit, cs_fabric_id; + u64 temp_addr_i; /* * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. @@ -939,11 +969,8 @@ static int denormalize_addr(struct addr_ctx *ctx) * bits there are. "intlv_addr_bit" tells us how many "Y" bits * there are (where "I" starts). */ - temp_addr_y = ctx->ret_addr & GENMASK_ULL(ctx->intlv_addr_bit - 1, 0); temp_addr_i = (ctx->cs_id << ctx->intlv_addr_bit); - temp_addr_x = (ctx->ret_addr & GENMASK_ULL(63, ctx->intlv_addr_bit)) - << num_intlv_bits; - ctx->ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; + ctx->ret_addr |= temp_addr_i; } return 0;