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Fri, 7 May 2021 19:01:59 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: Yazen Ghannam , linux-kernel@vger.kernel.org, tony.luck@intel.com, x86@kernel.org, Smita.KoralahalliChannabasappa@amd.com Subject: [PATCH 07/25] x86/MCE/AMD: Define function to add DRAM base and hole Date: Fri, 7 May 2021 15:01:22 -0400 Message-Id: <20210507190140.18854-8-Yazen.Ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210507190140.18854-1-Yazen.Ghannam@amd.com> References: <20210507190140.18854-1-Yazen.Ghannam@amd.com> X-Originating-IP: [165.204.25.250] X-ClientProxiedBy: BN6PR21CA0010.namprd21.prod.outlook.com (2603:10b6:404:8e::20) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from aus-x-yghannam.amd.com (165.204.25.250) by BN6PR21CA0010.namprd21.prod.outlook.com (2603:10b6:404:8e::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4129.3 via Frontend Transport; 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Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 45 ++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 263d419d4175..d1a6405bb990 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -938,14 +938,34 @@ static int denormalize_addr(struct addr_ctx *ctx) return 0; } -int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +static int add_base_and_hole(struct addr_ctx *ctx) { - u64 dram_base_addr, dram_limit_addr, dram_hole_base; + u64 dram_base_addr = (ctx->reg_base_addr & GENMASK_ULL(31, 12)) << 16; - u32 tmp; + /* Add dram base address */ + ctx->ret_addr += dram_base_addr; + + /* If legacy MMIO hole enabled */ + if (ctx->reg_base_addr & BIT(1)) { + u32 dram_hole_base; + + if (amd_df_indirect_read(ctx->nid, df_regs[DRAM_HOLE_CTL], + ctx->umc, &dram_hole_base)) + return -EINVAL; + + dram_hole_base &= GENMASK(31, 24); + if (ctx->ret_addr >= dram_hole_base) + ctx->ret_addr += (BIT_ULL(32) - dram_hole_base); + } + + return 0; +} + +int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +{ + u64 dram_limit_addr; u8 hashed_bit; - u8 lgcy_mmio_hole_en; struct addr_ctx ctx; @@ -971,23 +991,10 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) if (denormalize_addr(&ctx)) goto out_err; - lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); - dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16; - dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); - /* Add dram base address */ - ctx.ret_addr += dram_base_addr; - - /* If legacy MMIO hole enabled */ - if (lgcy_mmio_hole_en) { - if (amd_df_indirect_read(nid, df_regs[DRAM_HOLE_CTL], umc, &tmp)) - goto out_err; - - dram_hole_base = tmp & GENMASK(31, 24); - if (ctx.ret_addr >= dram_hole_base) - ctx.ret_addr += (BIT_ULL(32) - dram_hole_base); - } + if (add_base_and_hole(&ctx)) + goto out_err; if (ctx.hash_enabled) { /* Save some parentheses and grab ls-bit at the end. */