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[3/3] x86/mce: Add MCE priority for Accelerator devices

Message ID 20210511152538.148084-3-nchatrad@amd.com (mailing list archive)
State New, archived
Headers show
Series [1/3] x86/MCE/AMD, EDAC/mce_amd: Add new SMCA bank types. | expand

Commit Message

Naveen Krishna Chatradhi May 11, 2021, 3:25 p.m. UTC 
From: Mukul Joshi <mukul.joshi@amd.com>

Create a new MCE priority for accelerator devices on the
notifier chain. On some future AMD platforms, GPU devices
will process MCE errors and work as error detection
devices.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: John Clements <John.Clements@amd.com>
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
 arch/x86/include/asm/mce.h | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 8cbe7221a253..849f10a8602d 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -173,6 +173,7 @@  enum mce_notifier_prios {
 	MCE_PRIO_LOWEST,
 	MCE_PRIO_MCELOG,
 	MCE_PRIO_EDAC,
+	MCE_PRIO_ACCEL,
 	MCE_PRIO_NFIT,
 	MCE_PRIO_EXTLOG,
 	MCE_PRIO_UC,