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Wed, 23 Jun 2021 19:20:46 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, Smita.KoralahalliChannabasappa@amd.com, Yazen Ghannam Subject: [PATCH v2 09/31] EDAC/amd64: Define function to find interleaving mode Date: Wed, 23 Jun 2021 19:19:40 +0000 Message-Id: <20210623192002.3671647-10-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210623192002.3671647-1-yazen.ghannam@amd.com> References: <20210623192002.3671647-1-yazen.ghannam@amd.com> X-Originating-IP: [165.204.184.1] X-ClientProxiedBy: BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-ethanolx.amd.com (165.204.184.1) by BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Lr2Uc98ZhxLqPKz2HEfQ895j5jM10ais5w6D7sESFwwADlgwRojUo7S8yh033enXITF8776uPivVHZOhd/l07L+CyqFSxplYWYc+Wt3pj/GAwWvpXo8WoV9KA9530TDOjCGamZhfYvxxVLCq6zxaBvWFTq4WiqJOedGSv3pwEWktYmatG3nfzN6GyXke2602BXvngFMCwa9glgujJ4nnheXNzFNGCbhStL/I3pR6R8ZgPkcHs/LyO8uKG3mLtCzv4O0tnaSqkW/JzpMn6UQTnJKsYZvxg897X7190dhZB1AjNaVjBTmj+fFL/SAULwqIXPYVeRsIh9PqJjfhIlDJDsiQTwDSpRw1AA4+KfxHTriJA0f2QArWmsAuyDFIwWibsQJqbUA/o7mBEicomv1xE9MzM3G8hUblr/ihoZacCtTGRZ/jwCVbX6apbFkIFpyLTRhUK87k+GG2AYgjJxrN8ePkJQuV5hwFlOGvn8K7iBCN3jex/n4ahmLFXzicZAQXxD4M/Qdl25hELndg9fToMkNGokpUIfYZl2lsm5B3xFV3k6BOBctt92PDmSJc/KVf2Kj9sGzQGmUyyXSh2VJ9zptxaNowvXVHhEz4hUG3n+HWkqMOkZY4V72fFM8PKXrY4JJkVi2+SHNppxXv0fcY5HwC1kmtK3YAWMRdKfk+lVMgYhMYiY8/Fet7TmMY5Gd38f3MAmO0Jtv3A+3EIugQazibtzCmZJPzcm8HyOO+5CaCmg4nfC4LahKA5mkUcyVSEr0B8iefkKtvjxGazKvhlP+T2VzhwxaAAUCweJK1vHc/atEE2PPA3NCLAm4AzFsC4bU8SGMixZsM9C5LOaD094LYcEn4iOk91jZ9IHkEYuiiQeCAn/4YIbYm+ioMB2HYfc4sSHn/cpckBAjGskOcayn3FxHdi98ck9vF815U44bl5ScTKlIEJ+yzoB49N5JHTP0BJ+IPsyZYkQadfFrcJPzK5V+zFsgvyUKfryNViZTqVASgyC2GAF8ZoYSRGOU51+AHplvaZlFxpjXtTwd98mSLvefGmU5x76SV5sH4JeyJhjupgVpL6lyB68fujcrTOlO3Fjnc4VeUA+xnVWEBgXItfW8qaq6bo2ECgfT0eDxZg4kBZFTXiwEPkLNXMljWvzx5CiWJdSbGv4w2bzx0aFL6IKOu5Vwt9jvTJRbZQ5eVj+1NHZpzrwNJU/pNSiAp0CxLwrvWQaIsBnRwSEWHKSB/qdSiwTm4+48z+GugjHX8tg1i0u05skmDdef/QDcb1/JtX5hNQYWdCYQsVd736aVL/j2qYKf9u0Payqg9fbGg3C1lsXeaHJ3/j7O5zJnn X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 98d3f658-2783-4151-6d57-08d9367c0088 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2021 19:20:46.3930 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: f+SCa/yRfZtSIaUpyubsWED3U9rXOy6/f0aya0d1gBctxos9XaovKtFi4dHuy4EKs0RTHJpFo+AqGMU7wgwOZA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Define a helper function to find the interleaving mode. Define a DF2-specific function now. Future DF versions will have their own functions. Use an enumeration for the interleaving modes to give a human-readable value. Save the interleaving mode in the context struct, since this will be used in multiple functions. Multiple interleaving modes support hashing, so save a boolean in the context struct to check if hashing is enabled. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-6-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. * Add new function to data_fabric_ops. drivers/edac/amd64_edac.c | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 867ab32caab2..93a4ce9eb735 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1079,8 +1079,16 @@ static struct df_reg df_regs[] = { [SYS_FAB_ID_MASK] = {1, 0x208}, }; +/* These are mapped 1:1 to the hardware values. Special cases are set at > 0x20. */ +enum intlv_modes { + NONE = 0x00, + NOHASH_2CH = 0x01, + DF2_HASH_2CH = 0x21, +}; + /* Use "reg_" prefix for raw register values. */ struct addr_ctx { + enum intlv_modes intlv_mode; u64 ret_addr; u32 reg_dram_offset; u32 reg_base_addr; @@ -1088,10 +1096,12 @@ struct addr_ctx { u16 nid; u8 inst_id; u8 map_num; + bool hash_enabled; }; struct data_fabric_ops { u64 (*get_hi_addr_offset)(struct addr_ctx *ctx); + int (*get_intlv_mode)(struct addr_ctx *ctx); }; static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) @@ -1099,8 +1109,26 @@ static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; } +static int get_intlv_mode_df2(struct addr_ctx *ctx) +{ + ctx->intlv_mode = (ctx->reg_base_addr >> 4) & 0xF; + + if (ctx->intlv_mode == 8) { + ctx->intlv_mode = DF2_HASH_2CH; + ctx->hash_enabled = true; + } + + if (ctx->intlv_mode != NONE && + ctx->intlv_mode != NOHASH_2CH && + ctx->intlv_mode != DF2_HASH_2CH) + return -EINVAL; + + return 0; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = &get_hi_addr_offset_df2, + .get_intlv_mode = &get_intlv_mode_df2, }; struct data_fabric_ops *df_ops; @@ -1176,7 +1204,6 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr u8 num_intlv_bits, hashed_bit; u8 lgcy_mmio_hole_en; u8 cs_mask, cs_id = 0; - bool hash_enabled = false; struct addr_ctx ctx; @@ -1197,6 +1224,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (get_dram_addr_map(&ctx)) goto out_err; + if (df_ops->get_intlv_mode(&ctx)) + goto out_err; + lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); intlv_num_chan = (ctx.reg_base_addr >> 4) & 0xF; intlv_addr_sel = (ctx.reg_base_addr >> 8) & 0x7; @@ -1224,7 +1254,6 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr case 7: intlv_num_chan = 4; break; case 8: intlv_num_chan = 1; - hash_enabled = true; break; default: pr_err("%s: Invalid number of interleaved channels %d.\n", @@ -1325,7 +1354,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr ctx.ret_addr += (BIT_ULL(32) - dram_hole_base); } - if (hash_enabled) { + if (ctx.hash_enabled) { /* Save some parentheses and grab ls-bit at the end. */ hashed_bit = (ctx.ret_addr >> 12) ^ (ctx.ret_addr >> 18) ^