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Wed, 23 Jun 2021 19:20:47 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, Smita.KoralahalliChannabasappa@amd.com, Yazen Ghannam Subject: [PATCH v2 10/31] EDAC/amd64: Define function to denormalize address Date: Wed, 23 Jun 2021 19:19:41 +0000 Message-Id: <20210623192002.3671647-11-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210623192002.3671647-1-yazen.ghannam@amd.com> References: <20210623192002.3671647-1-yazen.ghannam@amd.com> X-Originating-IP: [165.204.184.1] X-ClientProxiedBy: BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-ethanolx.amd.com (165.204.184.1) by BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19 via Frontend Transport; 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This will be further refactored in later patches. Add the interleave address bit and the CS ID to the context struct. These values will be used by multiple functions. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-7-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 128 ++++++++++++++++++++++---------------- 1 file changed, 73 insertions(+), 55 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 93a4ce9eb735..ebb82b5e155b 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1096,6 +1096,8 @@ struct addr_ctx { u16 nid; u8 inst_id; u8 map_num; + u8 intlv_addr_bit; + u8 cs_id; bool hash_enabled; }; @@ -1193,57 +1195,26 @@ static int get_dram_addr_map(struct addr_ctx *ctx) return 0; } -static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +static int denormalize_addr(struct addr_ctx *ctx) { - u64 dram_base_addr, dram_limit_addr, dram_hole_base; u32 tmp; u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; - u8 intlv_addr_sel, intlv_addr_bit; - u8 num_intlv_bits, hashed_bit; - u8 lgcy_mmio_hole_en; - u8 cs_mask, cs_id = 0; - - struct addr_ctx ctx; - - memset(&ctx, 0, sizeof(ctx)); - - /* We start from the normalized address */ - ctx.ret_addr = norm_addr; - - ctx.nid = nid; - ctx.inst_id = umc; - - if (set_df_ops(&ctx)) - return -EINVAL; - - if (remove_dram_offset(&ctx)) - goto out_err; - - if (get_dram_addr_map(&ctx)) - goto out_err; - - if (df_ops->get_intlv_mode(&ctx)) - goto out_err; - - lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); - intlv_num_chan = (ctx.reg_base_addr >> 4) & 0xF; - intlv_addr_sel = (ctx.reg_base_addr >> 8) & 0x7; - dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16; + u8 intlv_addr_sel = (ctx->reg_base_addr >> 8) & 0x7; + u8 num_intlv_bits, cs_mask = 0; /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ if (intlv_addr_sel > 3) { pr_err("%s: Invalid interleave address select %d.\n", __func__, intlv_addr_sel); - goto out_err; + return -EINVAL; } - intlv_num_sockets = (ctx.reg_limit_addr >> 8) & 0x1; - intlv_num_dies = (ctx.reg_limit_addr >> 10) & 0x3; - dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); + intlv_num_sockets = (ctx->reg_limit_addr >> 8) & 0x1; + intlv_num_dies = (ctx->reg_limit_addr >> 10) & 0x3; - intlv_addr_bit = intlv_addr_sel + 8; + ctx->intlv_addr_bit = intlv_addr_sel + 8; /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ switch (intlv_num_chan) { @@ -1258,7 +1229,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr default: pr_err("%s: Invalid number of interleaved channels %d.\n", __func__, intlv_num_chan); - goto out_err; + return -EINVAL; } num_intlv_bits = intlv_num_chan; @@ -1266,7 +1237,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (intlv_num_dies > 2) { pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", __func__, intlv_num_dies); - goto out_err; + return -EINVAL; } num_intlv_bits += intlv_num_dies; @@ -1278,7 +1249,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (num_intlv_bits > 4) { pr_err("%s: Invalid interleave bits %d.\n", __func__, num_intlv_bits); - goto out_err; + return -EINVAL; } if (num_intlv_bits > 0) { @@ -1291,8 +1262,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr * umc/channel# as instance id of the coherent slave * for FICAA. */ - if (amd_df_indirect_read(nid, df_regs[FAB_BLK_INST_INFO_3], umc, &tmp)) - goto out_err; + if (amd_df_indirect_read(ctx->nid, df_regs[FAB_BLK_INST_INFO_3], + ctx->inst_id, &tmp)) + return -EINVAL; cs_fabric_id = (tmp >> 8) & 0xFF; die_id_bit = 0; @@ -1301,14 +1273,15 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr if (intlv_num_chan) { die_id_bit = intlv_num_chan; cs_mask = (1 << die_id_bit) - 1; - cs_id = cs_fabric_id & cs_mask; + ctx->cs_id = cs_fabric_id & cs_mask; } sock_id_bit = die_id_bit; if (intlv_num_dies || intlv_num_sockets) - if (amd_df_indirect_read(nid, df_regs[SYS_FAB_ID_MASK], umc, &tmp)) - goto out_err; + if (amd_df_indirect_read(ctx->nid, df_regs[SYS_FAB_ID_MASK], + ctx->inst_id, &tmp)) + return -EINVAL; /* If interleaved over more than 1 die. */ if (intlv_num_dies) { @@ -1316,7 +1289,8 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr die_id_shift = (tmp >> 24) & 0xF; die_id_mask = (tmp >> 8) & 0xFF; - cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; + ctx->cs_id |= ((cs_fabric_id & die_id_mask) + >> die_id_shift) << die_id_bit; } /* If interleaved over more than 1 socket. */ @@ -1324,7 +1298,8 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr socket_id_shift = (tmp >> 28) & 0xF; socket_id_mask = (tmp >> 16) & 0xFF; - cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; + ctx->cs_id |= ((cs_fabric_id & socket_id_mask) + >> socket_id_shift) << sock_id_bit; } /* @@ -1335,12 +1310,55 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr * bits there are. "intlv_addr_bit" tells us how many "Y" bits * there are (where "I" starts). */ - temp_addr_y = ctx.ret_addr & GENMASK_ULL(intlv_addr_bit - 1, 0); - temp_addr_i = (cs_id << intlv_addr_bit); - temp_addr_x = (ctx.ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; - ctx.ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; + temp_addr_y = ctx->ret_addr & GENMASK_ULL(ctx->intlv_addr_bit - 1, 0); + temp_addr_i = (ctx->cs_id << ctx->intlv_addr_bit); + temp_addr_x = (ctx->ret_addr & GENMASK_ULL(63, ctx->intlv_addr_bit)) + << num_intlv_bits; + ctx->ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; } + return 0; +} + +static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) +{ + u64 dram_base_addr, dram_limit_addr, dram_hole_base; + + u32 tmp; + + u8 hashed_bit; + u8 lgcy_mmio_hole_en; + + struct addr_ctx ctx; + + memset(&ctx, 0, sizeof(ctx)); + + /* We start from the normalized address */ + ctx.ret_addr = norm_addr; + + ctx.nid = nid; + ctx.inst_id = umc; + + if (set_df_ops(&ctx)) + return -EINVAL; + + if (remove_dram_offset(&ctx)) + return -EINVAL; + + if (get_dram_addr_map(&ctx)) + goto out_err; + + if (df_ops->get_intlv_mode(&ctx)) + goto out_err; + + if (denormalize_addr(&ctx)) + goto out_err; + + lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); + dram_base_addr = (ctx.reg_base_addr & GENMASK_ULL(31, 12)) << 16; + + dram_limit_addr = ((ctx.reg_limit_addr & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); + /* Add dram base address */ ctx.ret_addr += dram_base_addr; @@ -1360,12 +1378,12 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr (ctx.ret_addr >> 18) ^ (ctx.ret_addr >> 21) ^ (ctx.ret_addr >> 30) ^ - cs_id; + ctx.cs_id; hashed_bit &= BIT(0); - if (hashed_bit != ((ctx.ret_addr >> intlv_addr_bit) & BIT(0))) - ctx.ret_addr ^= BIT(intlv_addr_bit); + if (hashed_bit != ((ctx.ret_addr >> ctx.intlv_addr_bit) & BIT(0))) + ctx.ret_addr ^= BIT(ctx.intlv_addr_bit); } /* Is calculated system address is above DRAM limit address? */