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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2021 17:58:47.8246 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4191d8a9-4a9c-46f2-d0c7-08d99a3c977b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5030 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Some DF versions and interleaving modes require the DRAM base address and hole adjustments to be done before accounting for hashing. Others require this to be done after. Add a check for this behavior. Save a boolean in the ctx struct which can be appropriately set based on DF version or interleaving mode. Signed-off-by: Yazen Ghannam --- v2->v3: * New in v3. drivers/edac/amd64_edac.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 5dacd7e03202..07009901a283 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1092,6 +1092,7 @@ struct addr_ctx { u8 intlv_num_sockets; u8 cs_id; u8 node_id_shift; + bool late_hole_remove; int (*dehash_addr)(struct addr_ctx *ctx); void (*make_space_for_cs_id)(struct addr_ctx *ctx); void (*insert_cs_id)(struct addr_ctx *ctx); @@ -1638,12 +1639,15 @@ static int umc_normaddr_to_sysaddr(u64 *addr, u16 nid, u8 df_inst_id) if (denormalize_addr(&ctx)) return -EINVAL; - if (add_base_and_hole(&ctx)) + if (!ctx.late_hole_remove && add_base_and_hole(&ctx)) return -EINVAL; if (ctx.dehash_addr && ctx.dehash_addr(&ctx)) return -EINVAL; + if (ctx.late_hole_remove && add_base_and_hole(&ctx)) + return -EINVAL; + if (addr_over_limit(&ctx)) return -EINVAL;