@@ -1049,8 +1049,16 @@ static int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo)
return __df_indirect_read(node, func, reg, DF_BROADCAST, lo);
}
+/* These are mapped 1:1 to the hardware values. Special cases are set at > 0x20. */
+enum intlv_modes {
+ NONE = 0x00,
+ NOHASH_2CH = 0x01,
+ DF2_HASH_2CH = 0x21,
+};
+
/* Use "reg_" prefix for raw register values. */
struct addr_ctx {
+ enum intlv_modes intlv_mode;
u64 ret_addr;
u32 tmp;
u32 reg_dram_offset;
@@ -1059,10 +1067,12 @@ struct addr_ctx {
u16 nid;
u8 inst_id;
u8 map_num;
+ bool hash_enabled;
};
struct data_fabric_ops {
u64 (*get_hi_addr_offset) (struct addr_ctx *ctx);
+ int (*get_intlv_mode) (struct addr_ctx *ctx);
};
static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx)
@@ -1070,8 +1080,26 @@ static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx)
return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8;
}
+static int get_intlv_mode_df2(struct addr_ctx *ctx)
+{
+ ctx->intlv_mode = (ctx->reg_base_addr >> 4) & 0xF;
+
+ if (ctx->intlv_mode == 8) {
+ ctx->intlv_mode = DF2_HASH_2CH;
+ ctx->hash_enabled = true;
+ }
+
+ if (ctx->intlv_mode != NONE &&
+ ctx->intlv_mode != NOHASH_2CH &&
+ ctx->intlv_mode != DF2_HASH_2CH)
+ return -EINVAL;
+
+ return 0;
+}
+
struct data_fabric_ops df2_ops = {
.get_hi_addr_offset = get_hi_addr_offset_df2,
+ .get_intlv_mode = get_intlv_mode_df2,
};
struct data_fabric_ops *df_ops;
@@ -1136,7 +1164,6 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
u8 num_intlv_bits, hashed_bit;
u8 lgcy_mmio_hole_en;
u8 cs_mask, cs_id = 0;
- bool hash_enabled = false;
struct addr_ctx ctx;
@@ -1157,6 +1184,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
if (get_dram_addr_map(&ctx))
goto out_err;
+ if (df_ops->get_intlv_mode(&ctx))
+ goto out_err;
+
lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1);
intlv_num_chan = (ctx.reg_base_addr >> 4) & 0xF;
intlv_addr_sel = (ctx.reg_base_addr >> 8) & 0x7;
@@ -1184,7 +1214,6 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
case 7: intlv_num_chan = 4; break;
case 8: intlv_num_chan = 1;
- hash_enabled = true;
break;
default:
pr_err("%s: Invalid number of interleaved channels %d.\n",
@@ -1286,7 +1315,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
ctx.ret_addr += (BIT_ULL(32) - dram_hole_base);
}
- if (hash_enabled) {
+ if (ctx.hash_enabled) {
/* Save some parentheses and grab ls-bit at the end. */
hashed_bit = (ctx.ret_addr >> 12) ^
(ctx.ret_addr >> 18) ^
Define a helper function to find the interleaving mode. Define a DF2-specific function now. Future DF versions will have their own functions. Use an enumeration for the interleaving modes to give a human-readable value. Save the interleaving mode in the context struct, since this will be used in multiple functions. Multiple interleaving modes support hashing, so save a boolean in the context struct to check if hashing is enabled. This boolean will be replaced with a function pointer in a later patch. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> --- Link: https://lkml.kernel.org/r/20210623192002.3671647-10-yazen.ghannam@amd.com v2->v3: * Was patch 9 in v2. * Updated commit message. v1->v2: * Moved from arch/x86 to EDAC. * Add new function to data_fabric_ops. drivers/edac/amd64_edac.c | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-)