diff mbox series

[v3,2/6] x86/mce/inject: Set the valid bit in MCA_STATUS before error injection

Message ID 20211104215846.254012-3-Smita.KoralahalliChannabasappa@amd.com (mailing list archive)
State New, archived
Headers show
Series x86/mce: Handle error injection failures in mce-inject module | expand

Commit Message

Smita Koralahalli Nov. 4, 2021, 9:58 p.m. UTC 
MCA handlers check the valid bit in each status register (MCA_STATUS[Val])
and examine the remainder of the status register only if the valid bit is
set.

Set the valid bit unconditionally in the corresponding MCA_STATUS register
and correct any Val=0 injections made by the user.

Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Link: https://lkml.kernel.org/r/20211019233641.140275-3-Smita.KoralahalliChannabasappa@amd.com
---
v2:
	Added a warning statement instead of setting the valid bit.
v3:
	Reverted the changes and set the valid bit conditionally.
---
 arch/x86/kernel/cpu/mce/inject.c | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c
index fcec99e6c5d1..5e83a1ce7ac8 100644
--- a/arch/x86/kernel/cpu/mce/inject.c
+++ b/arch/x86/kernel/cpu/mce/inject.c
@@ -503,6 +503,8 @@  static void do_inject(void)
 
 	i_mce.tsc = rdtsc_ordered();
 
+	i_mce.status |= MCI_STATUS_VAL;
+
 	if (i_mce.misc)
 		i_mce.status |= MCI_STATUS_MISCV;