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Peter Anvin" , "Dave Hansen" , James Morse , Robert Richter , Yazen Ghannam , Smita Koralahalli Subject: [PATCH v4 2/3] x86/mce: Define function to extract ErrorAddr from MCA_ADDR Date: Fri, 25 Feb 2022 13:33:41 -0600 Message-ID: <20220225193342.215780-3-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220225193342.215780-1-Smita.KoralahalliChannabasappa@amd.com> References: <20220225193342.215780-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c38f2121-893c-4c86-461d-08d9f895c7cd X-MS-TrafficTypeDiagnostic: BN7PR12MB2627:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: InoF1STtfAsH9vqCgNFXb3dGhhIeOqF8uXF0I8glellVTla8SoPbW+Ea18RgH3TwR0Ijig9X10+tNkdsbaMJYIaVY9XYviTEAxkf9PEu/sY4LD2H1h53sdZyrxtpxgUaSOahH7nQGjK5UmMKIL6FWOMHmc24QvbEaJwGW7FpQGRzMFJxfn2ZWjWR7odcoSZIJoUxlICqF+AEwguygie52ESCMDCNvrXB9ylj3Lx8vC9GJDZsslq6SzaKrg+mmJtsQp21BDQ3y1SnD3rmtF2z34sjwdUV90A0OT+thFVElmpdQJ13YaLDqEIHvpbKfwC9cWWiTl3Uf3L1k9xQDZWj4fR2U7HU8BOgGcJHEFbzvko+VtstanOIleVIBfVDCrOVpaMsOATwmtdUsJzWEiOaF7v6KjHEJna8GVdNfKp1PY3PRQnAKgxmKkEqFpxktl3987DLgOcF2cbuGAilCZFtGX4WKht/lLxWfTnV1s9wMGk7Kvfy980eW66iNSJyNkgTCbYqJC7N1wNbmQ/5Mib0nOIsJJIJtXhjLxgmTdxAjoXTjl3MrOx4GbbMOXDnpVhTZNYvNB2n00ZhG3oLhA9DZ+Zi3WwDpbWJZNd8zAI/CWQLi8xANbqb6ITMMrezsdw6mIwOom08+/T6hDaBgeE5A6dmACX2T/QEHm2BR+UWBHRqJH9tsJklfFEtdaGYhw3PPx2hkvpY5nboPV3JFIcYYtKsMdObdukJxufqJA38e0C89wrbJ2joD1zFZtwOMFIDmjkpqo+O22sIRLjh/vvQ1CPFAEP05g0seY0ZtF7bu04= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(81166007)(2906002)(83380400001)(36756003)(40460700003)(356005)(86362001)(36860700001)(47076005)(966005)(82310400004)(8936002)(4326008)(26005)(7696005)(70586007)(110136005)(16526019)(316002)(1076003)(186003)(2616005)(8676002)(5660300002)(336012)(6666004)(54906003)(70206006)(426003)(508600001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Feb 2022 19:34:03.3695 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c38f2121-893c-4c86-461d-08d9f895c7cd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT043.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR12MB2627 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move MCA_ADDR[ErrorAddr] extraction into a separate helper function. This will be further refactored to support extended ErrorAddr bits in MCA_ADDR in newer AMD processors such as AMD 'Milan'. Signed-off-by: Smita Koralahalli Reviewed-by: Yazen Ghannam Signed-off-by: Smita Koralahalli Signed-off-by: Borislav Petkov Reviewed-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20220211223442.254489-2-Smita.KoralahalliChannabasappa@amd.com v2: No change. v3: Rebased on the latest tip tree. No functional changes. v4: Commit description change to be void of the patch linearity. --- arch/x86/include/asm/mce.h | 2 ++ arch/x86/kernel/cpu/mce/amd.c | 14 +++++++++----- arch/x86/kernel/cpu/mce/core.c | 7 ++----- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index cc73061e7255..99a4c32cbdfa 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -337,12 +337,14 @@ extern int mce_threshold_remove_device(unsigned int cpu); void mce_amd_feature_init(struct cpuinfo_x86 *c); enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank); +void smca_extract_err_addr(struct mce *m); #else static inline int mce_threshold_create_device(unsigned int cpu) { return 0; }; static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; }; static inline bool amd_mce_is_memory_error(struct mce *m) { return false; }; static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } +static inline void smca_extract_err_addr(struct mce *m) { } #endif static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); } diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 1940d305db1c..981d718851a2 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -722,6 +722,13 @@ bool amd_mce_is_memory_error(struct mce *m) return m->bank == 4 && xec == 0x8; } +void smca_extract_err_addr(struct mce *m) +{ + u8 lsb = (m->addr >> 56) & 0x3f; + + m->addr &= GENMASK_ULL(55, lsb); +} + static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) { struct mce m; @@ -740,11 +747,8 @@ static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) * Extract [55:] where lsb is the least significant * *valid* bit of the address bits. */ - if (mce_flags.smca) { - u8 lsb = (m.addr >> 56) & 0x3f; - - m.addr &= GENMASK_ULL(55, lsb); - } + if (mce_flags.smca) + smca_extract_err_addr(&m); } if (mce_flags.smca) { diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index c0e9aa9c8749..313058dc129f 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -645,11 +645,8 @@ static noinstr void mce_read_aux(struct mce *m, int i) * Extract [55:] where lsb is the least significant * *valid* bit of the address bits. */ - if (mce_flags.smca) { - u8 lsb = (m->addr >> 56) & 0x3f; - - m->addr &= GENMASK_ULL(55, lsb); - } + if (mce_flags.smca) + smca_extract_err_addr(m); } if (mce_flags.smca) {