diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index af6711cf03e9..e3b0a0329f43 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3716,7 +3716,17 @@ static bool f17_ecc_enabled(struct amd64_pvt *pvt)
 }
 
 static inline void
-f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt)
+f1x_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt)
+{
+	if (pvt->nbcap & NBCAP_SECDED)
+		mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
+
+	if (pvt->nbcap & NBCAP_CHIPKILL)
+		mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
+}
+
+static inline void
+f17_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt)
 {
 	u8 i, ecc_en = 1, cpk_en = 1, dev_x4 = 1, dev_x16 = 1;
 
@@ -3753,15 +3763,7 @@ static void setup_mci_misc_attrs(struct mem_ctl_info *mci)
 	mci->mtype_cap		= MEM_FLAG_DDR2 | MEM_FLAG_RDDR2;
 	mci->edac_ctl_cap	= EDAC_FLAG_NONE;
 
-	if (pvt->umc) {
-		f17h_determine_edac_ctl_cap(mci, pvt);
-	} else {
-		if (pvt->nbcap & NBCAP_SECDED)
-			mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
-
-		if (pvt->nbcap & NBCAP_CHIPKILL)
-			mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
-	}
+	pvt->ops->determine_edac_ctl_cap(mci, pvt);
 
 	mci->edac_cap		= pvt->ops->determine_edac_cap(pvt);
 	mci->mod_name		= EDAC_MOD_STR;
@@ -3801,6 +3803,7 @@ static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->get_mc_regs			= read_mc_regs;
 		pvt->ops->ecc_enabled			= f1x_ecc_enabled;
 		pvt->ops->determine_edac_cap		= f1x_determine_edac_cap;
+		pvt->ops->determine_edac_ctl_cap	= f1x_determine_edac_ctl_cap;
 		break;
 
 	case 0x10:
@@ -3817,6 +3820,7 @@ static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->get_mc_regs			= read_mc_regs;
 		pvt->ops->ecc_enabled			= f1x_ecc_enabled;
 		pvt->ops->determine_edac_cap		= f1x_determine_edac_cap;
+		pvt->ops->determine_edac_ctl_cap	= f1x_determine_edac_ctl_cap;
 		break;
 
 	case 0x15:
@@ -3849,6 +3853,7 @@ static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->get_mc_regs			= read_mc_regs;
 		pvt->ops->ecc_enabled			= f1x_ecc_enabled;
 		pvt->ops->determine_edac_cap		= f1x_determine_edac_cap;
+		pvt->ops->determine_edac_ctl_cap	= f1x_determine_edac_ctl_cap;
 		break;
 
 	case 0x16:
@@ -3871,6 +3876,7 @@ static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->get_mc_regs			= read_mc_regs;
 		pvt->ops->ecc_enabled			= f1x_ecc_enabled;
 		pvt->ops->determine_edac_cap		= f1x_determine_edac_cap;
+		pvt->ops->determine_edac_ctl_cap	= f1x_determine_edac_ctl_cap;
 		break;
 
 	case 0x17:
@@ -3907,6 +3913,7 @@ static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->get_mc_regs			= __read_mc_regs_df;
 		pvt->ops->ecc_enabled			= f17_ecc_enabled;
 		pvt->ops->determine_edac_cap		= f17_determine_edac_cap;
+		pvt->ops->determine_edac_ctl_cap	= f17_determine_edac_ctl_cap;
 
 		if (pvt->fam == 0x18) {
 			pvt->ctl_name			= "F18h";
@@ -3949,6 +3956,7 @@ static int per_family_init(struct amd64_pvt *pvt)
 		pvt->ops->get_mc_regs			= __read_mc_regs_df;
 		pvt->ops->ecc_enabled			= f17_ecc_enabled;
 		pvt->ops->determine_edac_cap		= f17_determine_edac_cap;
+		pvt->ops->determine_edac_ctl_cap	= f17_determine_edac_ctl_cap;
 		break;
 
 	default:
@@ -3961,7 +3969,7 @@ static int per_family_init(struct amd64_pvt *pvt)
 	    !pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects ||
 	    !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz ||
 	    !pvt->ops->get_mc_regs || !pvt->ops->ecc_enabled ||
-	    !pvt->ops->determine_edac_cap) {
+	    !pvt->ops->determine_edac_cap || !pvt->ops->determine_edac_ctl_cap) {
 		edac_dbg(1, "Common helper routines not defined.\n");
 		return -EFAULT;
 	}
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 9a789cb01f4d..0e0715a16981 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -471,6 +471,7 @@ struct low_ops {
 	void (*get_mc_regs)(struct amd64_pvt *pvt);
 	bool (*ecc_enabled)(struct amd64_pvt *pvt);
 	unsigned long (*determine_edac_cap)(struct amd64_pvt *pvt);
+	void (*determine_edac_ctl_cap)(struct mem_ctl_info *mci, struct amd64_pvt *pvt);
 };
 
 int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
