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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 16:14:31.7556 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9d54dd3d-7142-4aca-8535-08d9fad56756 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT021.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3555 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K Add function pointer for determine_ecc_sym_sz() in pvt->ops and assign family specific get_ecc_sym_sz() definitions appropriately. Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi --- This patch is created by splitting the 5/12th patch in series [v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/ drivers/edac/amd64_edac.c | 49 ++++++++++++++++++++++++--------------- drivers/edac/amd64_edac.h | 1 + 2 files changed, 31 insertions(+), 19 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 07428a6c7683..69c33eb17e4f 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3176,26 +3176,11 @@ static void free_mc_sibling_devs(struct amd64_pvt *pvt) } } -static void determine_ecc_sym_sz(struct amd64_pvt *pvt) +static void f1x_determine_ecc_sym_sz(struct amd64_pvt *pvt) { pvt->ecc_sym_sz = 4; - if (pvt->umc) { - u8 i; - - for_each_umc(i) { - /* Check enabled channels only: */ - if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { - if (pvt->umc[i].ecc_ctrl & BIT(9)) { - pvt->ecc_sym_sz = 16; - return; - } else if (pvt->umc[i].ecc_ctrl & BIT(7)) { - pvt->ecc_sym_sz = 8; - return; - } - } - } - } else if (pvt->fam >= 0x10) { + if (pvt->fam >= 0x10) { u32 tmp; amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); @@ -3209,6 +3194,26 @@ static void determine_ecc_sym_sz(struct amd64_pvt *pvt) } } +static void f17_determine_ecc_sym_sz(struct amd64_pvt *pvt) +{ + u8 i; + + pvt->ecc_sym_sz = 4; + + for_each_umc(i) { + /* Check enabled channels only: */ + if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { + if (pvt->umc[i].ecc_ctrl & BIT(9)) { + pvt->ecc_sym_sz = 16; + return; + } else if (pvt->umc[i].ecc_ctrl & BIT(7)) { + pvt->ecc_sym_sz = 8; + return; + } + } + } +} + /* * Retrieve the hardware registers of the memory controller. */ @@ -3312,7 +3317,7 @@ static void read_mc_regs(struct amd64_pvt *pvt) pvt->ops->determine_memory_type(pvt); edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); - determine_ecc_sym_sz(pvt); + pvt->ops->determine_ecc_sym_sz(pvt); } /* @@ -3786,6 +3791,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_base_mask = read_dct_base_mask; pvt->ops->prep_chip_selects = k8_prep_chip_selects; pvt->ops->determine_memory_type = f1x_determine_memory_type; + pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; break; case 0x10: @@ -3798,6 +3804,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_base_mask = read_dct_base_mask; pvt->ops->prep_chip_selects = default_prep_chip_selects; pvt->ops->determine_memory_type = f1x_determine_memory_type; + pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; break; case 0x15: @@ -3826,6 +3833,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow; pvt->ops->get_base_mask = read_dct_base_mask; pvt->ops->determine_memory_type = f1x_determine_memory_type; + pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; break; case 0x16: @@ -3844,6 +3852,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_base_mask = read_dct_base_mask; pvt->ops->prep_chip_selects = default_prep_chip_selects; pvt->ops->determine_memory_type = f1x_determine_memory_type; + pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz; break; case 0x17: @@ -3876,6 +3885,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_base_mask = read_umc_base_mask; pvt->ops->prep_chip_selects = f17_prep_chip_selects; pvt->ops->determine_memory_type = f17_determine_memory_type; + pvt->ops->determine_ecc_sym_sz = f17_determine_ecc_sym_sz; if (pvt->fam == 0x18) { pvt->ctl_name = "F18h"; @@ -3914,6 +3924,7 @@ static int per_family_init(struct amd64_pvt *pvt) pvt->ops->get_base_mask = read_umc_base_mask; pvt->ops->prep_chip_selects = f17_prep_chip_selects; pvt->ops->determine_memory_type = f17_determine_memory_type; + pvt->ops->determine_ecc_sym_sz = f17_determine_ecc_sym_sz; break; default: @@ -3924,7 +3935,7 @@ static int per_family_init(struct amd64_pvt *pvt) /* ops required for all the families */ if (!pvt->ops->early_channel_count || !pvt->ops->dbam_to_cs || !pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects || - !pvt->ops->determine_memory_type) { + !pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz) { edac_dbg(1, "Common helper routines not defined.\n"); return -EFAULT; } diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 4d8830b8afa2..f6769148d8b7 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -467,6 +467,7 @@ struct low_ops { void (*get_base_mask)(struct amd64_pvt *pvt); void (*prep_chip_selects)(struct amd64_pvt *pvt); void (*determine_memory_type)(struct amd64_pvt *pvt); + void (*determine_ecc_sym_sz)(struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,