| Message ID | 20220414102813.4468-1-shubhrajyoti.datta@xilinx.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3] edac: synopsys: Fix the issue in reporting of the error count | expand |
On 4/14/22 12:28, Shubhrajyoti Datta wrote: > Currently the error count from status register is being read which > is not correct. Fix the issue by reading the count from the > error count register(ERRCNT). > > Fixes: b500b4a029d5 ("EDAC, synopsys: Add ECC support for ZynqMP DDR controller") > Cc: <stable@vger.kernel.org> > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > --- > v2: > Remove the cumulative count change > v3: > Add the fixes and stable tag > > drivers/edac/synopsys_edac.c | 15 +++++++++++---- > 1 file changed, 11 insertions(+), 4 deletions(-) > > diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c > index f05ff02c0656..1a9a5b886903 100644 > --- a/drivers/edac/synopsys_edac.c > +++ b/drivers/edac/synopsys_edac.c > @@ -164,6 +164,11 @@ > #define ECC_STAT_CECNT_SHIFT 8 > #define ECC_STAT_BITNUM_MASK 0x7F > > +/* ECC error count register definitions */ > +#define ECC_ERRCNT_UECNT_MASK 0xFFFF0000 > +#define ECC_ERRCNT_UECNT_SHIFT 16 > +#define ECC_ERRCNT_CECNT_MASK 0xFFFF > + > /* DDR QOS Interrupt register definitions */ > #define DDR_QOS_IRQ_STAT_OFST 0x20200 > #define DDR_QOSUE_MASK 0x4 > @@ -423,14 +428,16 @@ static int zynqmp_get_error_info(struct synps_edac_priv *priv) > base = priv->baseaddr; > p = &priv->stat; > > + regval = readl(base + ECC_ERRCNT_OFST); > + p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK; > + p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT; > + if (!p->ce_cnt) > + goto ue_err; > + > regval = readl(base + ECC_STAT_OFST); > if (!regval) > return 1; > > - p->ce_cnt = (regval & ECC_STAT_CECNT_MASK) >> ECC_STAT_CECNT_SHIFT; > - p->ue_cnt = (regval & ECC_STAT_UECNT_MASK) >> ECC_STAT_UECNT_SHIFT; > - if (!p->ce_cnt) > - goto ue_err; > > p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK); > Acked-by: Michal Simek <michal.simek@xilinx.com> M
On Thu, Apr 14, 2022 at 03:58:13PM +0530, Shubhrajyoti Datta wrote: > Currently the error count from status register is being read which > is not correct. Fix the issue by reading the count from the > error count register(ERRCNT). > > Fixes: b500b4a029d5 ("EDAC, synopsys: Add ECC support for ZynqMP DDR controller") > Cc: <stable@vger.kernel.org> > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > --- > v2: > Remove the cumulative count change > v3: > Add the fixes and stable tag > > drivers/edac/synopsys_edac.c | 15 +++++++++++---- > 1 file changed, 11 insertions(+), 4 deletions(-) > > diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c > index f05ff02c0656..1a9a5b886903 100644 > --- a/drivers/edac/synopsys_edac.c > +++ b/drivers/edac/synopsys_edac.c > @@ -164,6 +164,11 @@ > #define ECC_STAT_CECNT_SHIFT 8 > #define ECC_STAT_BITNUM_MASK 0x7F > > +/* ECC error count register definitions */ > +#define ECC_ERRCNT_UECNT_MASK 0xFFFF0000 > +#define ECC_ERRCNT_UECNT_SHIFT 16 > +#define ECC_ERRCNT_CECNT_MASK 0xFFFF > + > /* DDR QOS Interrupt register definitions */ > #define DDR_QOS_IRQ_STAT_OFST 0x20200 > #define DDR_QOSUE_MASK 0x4 > @@ -423,14 +428,16 @@ static int zynqmp_get_error_info(struct synps_edac_priv *priv) > base = priv->baseaddr; > p = &priv->stat; > > + regval = readl(base + ECC_ERRCNT_OFST); > + p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK; > + p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT; > + if (!p->ce_cnt) > + goto ue_err; > + > regval = readl(base + ECC_STAT_OFST); > if (!regval) > return 1; > > - p->ce_cnt = (regval & ECC_STAT_CECNT_MASK) >> ECC_STAT_CECNT_SHIFT; > - p->ue_cnt = (regval & ECC_STAT_UECNT_MASK) >> ECC_STAT_UECNT_SHIFT; > - if (!p->ce_cnt) > - goto ue_err; > > p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK); > > -- Applied, thanks.
diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index f05ff02c0656..1a9a5b886903 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -164,6 +164,11 @@ #define ECC_STAT_CECNT_SHIFT 8 #define ECC_STAT_BITNUM_MASK 0x7F +/* ECC error count register definitions */ +#define ECC_ERRCNT_UECNT_MASK 0xFFFF0000 +#define ECC_ERRCNT_UECNT_SHIFT 16 +#define ECC_ERRCNT_CECNT_MASK 0xFFFF + /* DDR QOS Interrupt register definitions */ #define DDR_QOS_IRQ_STAT_OFST 0x20200 #define DDR_QOSUE_MASK 0x4 @@ -423,14 +428,16 @@ static int zynqmp_get_error_info(struct synps_edac_priv *priv) base = priv->baseaddr; p = &priv->stat; + regval = readl(base + ECC_ERRCNT_OFST); + p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK; + p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT; + if (!p->ce_cnt) + goto ue_err; + regval = readl(base + ECC_STAT_OFST); if (!regval) return 1; - p->ce_cnt = (regval & ECC_STAT_CECNT_MASK) >> ECC_STAT_CECNT_SHIFT; - p->ue_cnt = (regval & ECC_STAT_UECNT_MASK) >> ECC_STAT_UECNT_SHIFT; - if (!p->ce_cnt) - goto ue_err; p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK);
Currently the error count from status register is being read which is not correct. Fix the issue by reading the count from the error count register(ERRCNT). Fixes: b500b4a029d5 ("EDAC, synopsys: Add ECC support for ZynqMP DDR controller") Cc: <stable@vger.kernel.org> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> --- v2: Remove the cumulative count change v3: Add the fixes and stable tag drivers/edac/synopsys_edac.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-)