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Tue, 3 May 2022 03:28:34 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT054.mail.protection.outlook.com (10.13.177.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5206.12 via Frontend Transport; Tue, 3 May 2022 03:28:34 +0000 Received: from ethanolx50f7host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Mon, 2 May 2022 22:28:33 -0500 From: Smita Koralahalli To: , , CC: Tony Luck , Smita Koralahalli , , Yazen Ghannam , Dave Hansen , "Borislav Petkov" Subject: [PATCH v5 1/3] x86/mce/mce-inject: Replace struct i_mce with struct inject_desc Date: Mon, 2 May 2022 22:28:17 -0500 Message-ID: <20220503032820.61667-2-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220503032820.61667-1-Smita.KoralahalliChannabasappa@amd.com> References: <20220503032820.61667-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5250bd70-bf89-4648-10ed-08da2cb50141 X-MS-TrafficTypeDiagnostic: PH7PR12MB5877:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2022 03:28:34.7309 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5250bd70-bf89-4648-10ed-08da2cb50141 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5877 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Replace the existing struct i_mce with struct inject_desc. Extend the struct to include "error" field. This error field will be useful to return error codes to userspace when error injection fails. Suggested-by: Borislav Petkov Signed-off-by: Borislav Petkov Signed-off-by: Smita Koralahalli Link: https://lkml.kernel.org/r/Yk267A1MKOo2AlXQ@zn.tnic --- arch/x86/kernel/cpu/mce/inject.c | 94 ++++++++++++++++++-------------- 1 file changed, 52 insertions(+), 42 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c index 5fbd7ffb3233..05581b718529 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -33,10 +33,12 @@ #include "internal.h" -/* - * Collect all the MCi_XXX settings - */ -static struct mce i_mce; +/* Collect all the MCi_XXX settings */ +static struct inject_desc { + struct mce m; + int err; +} inj_desc; + static struct dentry *dfs_inj; #define MAX_FLAG_OPT_SIZE 4 @@ -110,9 +112,11 @@ static int inj_ipid_set(void *data, u64 val) DEFINE_SIMPLE_ATTRIBUTE(ipid_fops, inj_ipid_get, inj_ipid_set, "%llx\n"); -static void setup_inj_struct(struct mce *m) +static void setup_inj_struct(void) { - memset(m, 0, sizeof(struct mce)); + struct mce *m = &inj_desc.m; + + memset(&inj_desc, 0, sizeof(struct inject_desc)); m->cpuvendor = boot_cpu_data.x86_vendor; m->time = ktime_get_real_seconds(); @@ -470,56 +474,57 @@ static void toggle_nb_mca_mst_cpu(u16 nid) __func__, PCI_FUNC(F3->devfn), NBCFG); } -static void prepare_msrs(void *info) +static void prepare_msrs(void *unused) { - struct mce m = *(struct mce *)info; - u8 b = m.bank; + struct mce *m = &inj_desc.m; + u8 b = inj_desc.m.bank; - wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); + wrmsrl(MSR_IA32_MCG_STATUS, m->mcgstatus); if (boot_cpu_has(X86_FEATURE_SMCA)) { - if (m.inject_flags == DFR_INT_INJ) { - wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); - wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); + if (m->inject_flags == DFR_INT_INJ) { + wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m->status); + wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m->addr); } else { - wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); - wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); + wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m->status); + wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m->addr); } - wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); - wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); + wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m->misc); + wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m->synd); } else { - wrmsrl(MSR_IA32_MCx_STATUS(b), m.status); - wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); - wrmsrl(MSR_IA32_MCx_MISC(b), m.misc); + wrmsrl(MSR_IA32_MCx_STATUS(b), m->status); + wrmsrl(MSR_IA32_MCx_ADDR(b), m->addr); + wrmsrl(MSR_IA32_MCx_MISC(b), m->misc); } } -static void do_inject(void) +static int do_inject(void) { + struct mce *m = &inj_desc.m; + unsigned int cpu = m->extcpu; u64 mcg_status = 0; - unsigned int cpu = i_mce.extcpu; - u8 b = i_mce.bank; + u8 b = m->bank; - i_mce.tsc = rdtsc_ordered(); + m->tsc = rdtsc_ordered(); - i_mce.status |= MCI_STATUS_VAL; + m->status |= MCI_STATUS_VAL; - if (i_mce.misc) - i_mce.status |= MCI_STATUS_MISCV; + if (m->misc) + m->status |= MCI_STATUS_MISCV; - if (i_mce.synd) - i_mce.status |= MCI_STATUS_SYNDV; + if (m->synd) + m->status |= MCI_STATUS_SYNDV; if (inj_type == SW_INJ) { - mce_log(&i_mce); - return; + mce_log(m); + return 0; } /* prep MCE global settings for the injection */ mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV; - if (!(i_mce.status & MCI_STATUS_PCC)) + if (!(m->status & MCI_STATUS_PCC)) mcg_status |= MCG_STATUS_RIPV; /* @@ -528,8 +533,8 @@ static void do_inject(void) * - MCx_STATUS[UC] cleared: deferred errors are _not_ UC */ if (inj_type == DFR_INT_INJ) { - i_mce.status |= MCI_STATUS_DEFERRED; - i_mce.status &= ~MCI_STATUS_UC; + m->status |= MCI_STATUS_DEFERRED; + m->status &= ~MCI_STATUS_UC; } /* @@ -550,12 +555,15 @@ static void do_inject(void) toggle_hw_mce_inject(cpu, true); - i_mce.mcgstatus = mcg_status; - i_mce.inject_flags = inj_type; - smp_call_function_single(cpu, prepare_msrs, &i_mce, 0); + m->mcgstatus = mcg_status; + m->inject_flags = inj_type; + smp_call_function_single(cpu, prepare_msrs, NULL, 0); toggle_hw_mce_inject(cpu, false); + if (inj_desc.err) + goto err; + switch (inj_type) { case DFR_INT_INJ: smp_call_function_single(cpu, trigger_dfr_int, NULL, 0); @@ -570,6 +578,7 @@ static void do_inject(void) err: cpus_read_unlock(); + return inj_desc.err; } /* @@ -580,6 +589,7 @@ static int inj_bank_set(void *data, u64 val) { struct mce *m = (struct mce *)data; u8 n_banks; + int err; u64 cap; /* Get bank count on target CPU so we can handle non-uniform values. */ @@ -619,12 +629,12 @@ static int inj_bank_set(void *data, u64 val) } inject: - do_inject(); + err = do_inject(); /* Reset injection struct */ - setup_inj_struct(&i_mce); + setup_inj_struct(); - return 0; + return err; } MCE_INJECT_GET(bank); @@ -714,7 +724,7 @@ static void __init debugfs_init(void) for (i = 0; i < ARRAY_SIZE(dfs_fls); i++) debugfs_create_file(dfs_fls[i].name, dfs_fls[i].perm, dfs_inj, - &i_mce, dfs_fls[i].fops); + &inj_desc.m, dfs_fls[i].fops); } static int __init inject_init(void) @@ -727,7 +737,7 @@ static int __init inject_init(void) register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0, "mce_notify"); mce_register_injector_chain(&inject_nb); - setup_inj_struct(&i_mce); + setup_inj_struct(); pr_info("Machine check injector initialized\n");