diff mbox series

EDAC/xgene: fix typo in comment

Message ID 20220521111145.81697-39-Julia.Lawall@inria.fr (mailing list archive)
State New, archived
Headers show
Series EDAC/xgene: fix typo in comment | expand

Commit Message

Julia Lawall May 21, 2022, 11:10 a.m. UTC
Spelling mistake (triple letters) in comment.
Detected with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>

---
 drivers/edac/xgene_edac.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Borislav Petkov May 21, 2022, 2:07 p.m. UTC | #1
On Sat, May 21, 2022 at 01:10:49PM +0200, Julia Lawall wrote:
> Spelling mistake (triple letters) in comment.
> Detected with the help of Coccinelle.
> 
> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
> 
> ---
>  drivers/edac/xgene_edac.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/edac/xgene_edac.c b/drivers/edac/xgene_edac.c
> index 7197f9fa0245..54081403db4f 100644
> --- a/drivers/edac/xgene_edac.c
> +++ b/drivers/edac/xgene_edac.c
> @@ -501,7 +501,7 @@ static int xgene_edac_mc_remove(struct xgene_edac_mc_ctx *mcu)
>  #define MEMERR_L2C_L2ESRA_PAGE_OFFSET		0x0804
>  
>  /*
> - * Processor Module Domain (PMD) context - Context for a pair of processsors.
> + * Processor Module Domain (PMD) context - Context for a pair of processors.
>   * Each PMD consists of 2 CPUs and a shared L2 cache. Each CPU consists of
>   * its own L1 cache.
>   */

Applied, thanks.
diff mbox series

Patch

diff --git a/drivers/edac/xgene_edac.c b/drivers/edac/xgene_edac.c
index 7197f9fa0245..54081403db4f 100644
--- a/drivers/edac/xgene_edac.c
+++ b/drivers/edac/xgene_edac.c
@@ -501,7 +501,7 @@  static int xgene_edac_mc_remove(struct xgene_edac_mc_ctx *mcu)
 #define MEMERR_L2C_L2ESRA_PAGE_OFFSET		0x0804
 
 /*
- * Processor Module Domain (PMD) context - Context for a pair of processsors.
+ * Processor Module Domain (PMD) context - Context for a pair of processors.
  * Each PMD consists of 2 CPUs and a shared L2 cache. Each CPU consists of
  * its own L1 cache.
  */