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Peter Anvin" , Yazen Ghannam , "Smita Koralahalli" , Borislav Petkov Subject: [PATCH] x86/mce: Check whether writes to MCA_STATUS are getting ignored Date: Mon, 27 Jun 2022 20:56:46 +0000 Message-ID: <20220627205646.4692-1-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5b72edb1-1096-49e4-f368-08da587f992e X-MS-TrafficTypeDiagnostic: BY5PR12MB3649:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Yq5hRQKpY/pbbnx/3IykDOaqS4ejURHC7ke1wBAkmpMecJHywoqA1jJCmeucXwBbK+/c7mbLuiOlEvPUhfWnQny9kzu39H9xwyjzSMmvXPt8SEpOZSQJ1IqFC81/Kf/WRX+D98jstrPTk2IjBqlI76mYHX9igK2RhY0uAv4iO6XVcnlHlfO5p2lN5EQhZahmdlL0vt/JmMASfKZtO4m4NDwSBWpHGnnVyZYIq5ZnbQDlP7C4pvm+hdZBsGCo+Esx1pNDbrEOhLaQOsSOEWbfZzmnmBjMNg+XgGIzIcdzFwXnPMYUl4rsmkL0wjbLlqKiJAH6mKkM2A/ovOMF9Xn1OqDsrccW6qdc/T7oIvFMBei+phnNWGHyNHngRYhUTrzKcy0vV0i4bBDvFFxCkwUUfQrgKlKmpHraX8E1czZ5xmafGO4t2mhSVBfdqYpApu9TtGTEDaOYJ8x1RQI+myoL47qdpK9Luq9mygHgRcoc/t86bjcl7TvLSHEN8nJjj26dh3bkgc9/AZ5KI9FDTy/eZ/Ec50/CljceTbvXIl2RWnuIbTLHIWP9fV9AsfhFavbbsfEWHbRzjJvj2dW/5EvONVxEyn3mPj0pm/zKaUCP20WeHfXRXatD7wIvburofRe9EuHeQbXQOXL/55eb50aLfC+fQ/WQaUpIrRvrQtim17/NNI3geKjd5tBn0gdE0ZoM4ed+o3WAnj1dWcThjxTojZ6oNLXzQNjOt2m9oHLl7r+Bc4GIIUPLcHNHCZNGHZrBlowVwK/eEzONXP5VH0YQ/nqeeLpONb7sPXMvxcGuEEut8BWC+QdS5+VR2z2EiLW9awBamOSxsKQRam7urA0GJ3fK6S9Vog3NHWxrzv6nlQ1LpJ1JLBb2/xNNKB38eD6oUSVgVuw4rRW+TvHycudee0UR7qYuL8gy53aS+8g4Ito= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(39860400002)(376002)(346002)(396003)(136003)(36840700001)(40470700004)(46966006)(40460700003)(47076005)(426003)(6666004)(81166007)(336012)(82740400003)(2616005)(316002)(40480700001)(186003)(1076003)(16526019)(70586007)(5660300002)(36756003)(6916009)(8676002)(54906003)(7696005)(2906002)(70206006)(356005)(82310400005)(966005)(8936002)(4326008)(478600001)(36860700001)(26005)(83380400001)(41300700001)(86362001)(21314003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2022 20:57:07.9803 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b72edb1-1096-49e4-f368-08da587f992e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT057.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3649 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The platform can sometimes - depending on its settings - cause writes to MCA_STATUS MSRs to get ignored, regardless of HWCR[McStatusWrEn]'s value. For further info see PPR for AMD Family 19h, Model 01h, Revision B1 Processors, doc ID 55898 at https://bugzilla.kernel.org/show_bug.cgi?id=206537. Therefore, probe for ignored writes to MCA_STATUS to determine if hardware error injection is at all possible. [ bp: Heavily massage commit message and patch. ] Signed-off-by: Smita Koralahalli Signed-off-by: Borislav Petkov Link: https://lore.kernel.org/r/20220214233640.70510-2-Smita.KoralahalliChannabasappa@amd.com --- arch/x86/kernel/cpu/mce/inject.c | 47 ++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/mce/internal.h | 2 +- 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c index 5fbd7ffb3233..12cf2e7ca33c 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -33,6 +33,8 @@ #include "internal.h" +static bool hw_injection_possible = true; + /* * Collect all the MCi_XXX settings */ @@ -339,6 +341,8 @@ static int __set_inj(const char *buf) for (i = 0; i < N_INJ_TYPES; i++) { if (!strncmp(flags_options[i], buf, strlen(flags_options[i]))) { + if (i > SW_INJ && !hw_injection_possible) + continue; inj_type = i; return 0; } @@ -717,11 +721,54 @@ static void __init debugfs_init(void) &i_mce, dfs_fls[i].fops); } +static void check_hw_inj_possible(void) +{ + int cpu; + u8 bank; + + /* + * This behavior exists only on SMCA systems though its not directly + * related to SMCA. + */ + if (!cpu_feature_enabled(X86_FEATURE_SMCA)) + return; + + cpu = get_cpu(); + + for (bank = 0; bank < MAX_NR_BANKS; ++bank) { + u64 status = MCI_STATUS_VAL, ipid; + + /* Check whether bank is populated */ + rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), ipid); + if (!ipid) + continue; + + toggle_hw_mce_inject(cpu, true); + + wrmsrl_safe(mca_msr_reg(bank, MCA_STATUS), status); + rdmsrl_safe(mca_msr_reg(bank, MCA_STATUS), &status); + + if (!status) { + hw_injection_possible = false; + pr_warn("Platform does not allow *hardware* error injection." + "Try using APEI EINJ instead.\n"); + } + + toggle_hw_mce_inject(cpu, false); + + break; + } + + put_cpu(); +} + static int __init inject_init(void) { if (!alloc_cpumask_var(&mce_inject_cpumask, GFP_KERNEL)) return -ENOMEM; + check_hw_inj_possible(); + debugfs_init(); register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0, "mce_notify"); diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 4ae0e603f7fa..7e03f5b7f6bd 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -211,7 +211,7 @@ noinstr u64 mce_rdmsrl(u32 msr); static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg) { - if (mce_flags.smca) { + if (cpu_feature_enabled(X86_FEATURE_SMCA)) { switch (reg) { case MCA_CTL: return MSR_AMD64_SMCA_MCx_CTL(bank); case MCA_ADDR: return MSR_AMD64_SMCA_MCx_ADDR(bank);