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Mon, 22 Aug 2022 04:58:43 -0700 Received: from xhdlakshmis40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Mon, 22 Aug 2022 06:58:39 -0500 From: Sai Krishna Potthuri To: Rob Herring , Krzysztof Kozlowski , Michal Simek , Borislav Petkov , Mauro Carvalho Chehab , Tony Luck , James Morse , "Robert Richter" CC: , , , , , , Shubhrajyoti Datta , Sai Krishna Potthuri Subject: [PATCH v2 1/2] dt-bindings: edac: Add bindings for Xilinx ZynqMP OCM Date: Mon, 22 Aug 2022 17:28:20 +0530 Message-ID: <20220822115821.3907-2-sai.krishna.potthuri@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220822115821.3907-1-sai.krishna.potthuri@amd.com> References: <20220822115821.3907-1-sai.krishna.potthuri@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f6dce733-2cc1-439f-e98f-08da8435aaf6 X-MS-TrafficTypeDiagnostic: BL0PR12MB5506:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2022 11:58:46.2006 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f6dce733-2cc1-439f-e98f-08da8435aaf6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB5506 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Shubhrajyoti Datta Add bindings for Xilinx ZynqMP OCM controller. Signed-off-by: Shubhrajyoti Datta Signed-off-by: Sai Krishna Potthuri --- .../bindings/edac/xlnx,zynqmp-ocmc.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/xlnx,zynqmp-ocmc.yaml diff --git a/Documentation/devicetree/bindings/edac/xlnx,zynqmp-ocmc.yaml b/Documentation/devicetree/bindings/edac/xlnx,zynqmp-ocmc.yaml new file mode 100644 index 000000000000..6389fcb7ed69 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/xlnx,zynqmp-ocmc.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/xlnx,zynqmp-ocmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Zynqmp OCM(On-Chip Memory) Controller + +maintainers: + - Shubhrajyoti Datta + - Sai Krishna Potthuri + +description: | + The OCM supports 64-bit wide ECC functionality to detect multi-bit errors + and recover from a single-bit memory fault.On a write, if all bytes are + being written, the ECC is generated and written into the ECC RAM along with + the write-data that is written into the data RAM. If one or more bytes are + not written, then the read operation results in an correctable error or + uncorrectable error. + +properties: + compatible: + const: xlnx,zynqmp-ocmc-1.0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + memory-controller@ff960000 { + compatible = "xlnx,zynqmp-ocmc-1.0"; + reg = <0xff960000 0x1000>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + };