@@ -10,6 +10,7 @@
#include <linux/bitfield.h>
#include <linux/edac.h>
#include <linux/fs.h>
+#include <linux/log2.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
@@ -357,6 +358,27 @@ struct snps_edac_priv {
#endif
};
+/**
+ * snps_get_bitpos - Get DQ-bus corrected bit position.
+ * @bitnum: Bit number retrieved from the ECCSTAT.corrected_bit_num field.
+ * @dq_width: Controller DQ-bus width.
+ *
+ * Return: actual corrected DQ-bus bit position starting from 0.
+ */
+static inline u32 snps_get_bitpos(u32 bitnum, enum snps_dq_width dq_width)
+{
+ /* ecc[0] bit */
+ if (bitnum == 0)
+ return BITS_PER_BYTE << dq_width;
+
+ /* ecc[1:x] bit */
+ if (is_power_of_2(bitnum))
+ return (BITS_PER_BYTE << dq_width) + ilog2(bitnum) + 1;
+
+ /* data[0:y] bit */
+ return bitnum - ilog2(bitnum) - 2;
+}
+
/**
* snps_get_error_info - Get the current ECC error info.
* @priv: DDR memory controller private instance data.
@@ -385,6 +407,8 @@ static int snps_get_error_info(struct snps_edac_priv *priv)
if (!p->ce_cnt)
goto ue_err;
+ p->ceinfo.bitpos = snps_get_bitpos(p->ceinfo.bitpos, priv->info.dq_width);
+
regval = readl(base + ECC_CEADDR0_OFST);
p->ceinfo.row = FIELD_GET(ECC_CEADDR0_ROW_MASK, regval);
Since the DQ-bus width is now available in the driver we can use it to calculate the bit-position corrected by the ECC engine. It can be done based on the offsets provided in the table [1]. Using info from that table let's introduce a new inline method snps_get_bitpos() which would provide the actual CE bit-position based on the value read from the ECCSTAT.corrected_bit_num field and the DQ-bus width. The method will be called if a corrected error is detected. [1] DesignWare® Cores Enhanced Universal DDR Memory Controller (uMCTL2) Databook, Version 3.91a, October 2020, p.426-427 Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> --- drivers/edac/synopsys_edac.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)